Hid - XMOS xCORE-200 Multi-channel Audio board Design Manual

USB Audio Design Guide
L8A-64-TQ128
Figure 35:
Audio Clock
Connections
CODEC mode
Single-Speed
Figure 36:
CODEC Double-Speed
Modes
Quad-Speed
The internal master clock dividers are set using the MDIV pins. MDIV is tied low
and MDIV2 is connected to bit 2 of port 32A (as well as to the master clock select).
With MDIV2 low, the master clock must be 256Fs in single-speed mode, 128Fs in
double-speed mode and 64Fs in quad-speed mode. This allows an 11.2896MHz
master clock to be used for sample rates of 44.1, 88.2 and 176.4kHz.
With MDIV2 high, the master clock must be 512Fs in single-speed mode, 256Fs
in double-speed mode and 128Fs in quad-speed mode. This allows a 24.576MHz
master clock to be used for sample rates of 48, 96 and 192kHz.
When changing sample frequency, the CodecConfig() function first puts the CODEC
into reset by setting P32A[1] low. It selects the required master clock/CODEC
dividers and keeps the CODEC in reset for 1ms to allow the clocks to stabilize. The
CODEC is brought out of reset by setting P32A[1] back high.

6.1.3 HID

The reference design implements basic HID controls.
vendor_ReadHidButtons() simply reads from buttons A and B and returns their
state in the relevant bits depending on the desired functionality (play/pause/skip
etc). Note the buttons are active low, the HID controls active high. The buttons are
therefore read and then inverted.
XM0088546.1
BCLK
LR CLK
SDOUT
SDIN
MCLK
MCLK_SEL
24.576 MHz 11.2896 MHz
Crystal
CODEC sample rate range (kHz)
4-54
50-108
100-216
Codec
CS427
0
Crystal
66/110
The call to