XMOS xCORE-200 Quick Start Manual

xCORE-200 Clock Frequency Control
IN TH I S D OCU MENT
PLL and Clock Divider Overview
Constraints
PLL Settings
Configuring the xCORE-200 Device
Frequency Control Registers
Example PLL Configurations
Example System Clock Divider Configurations
Configuring the Clock System Through the XN File
Document History
1 PLL and Clock Divider Overview
A low frequency external clock is used to drive the internal phase locked loop (PLL)
of xCORE-200 devices and obtain the system clock. A number of system clock
dividers are then used on the system clock to derive the clocks for the xCORE tiles,
the RGMII unit, the switch and the reference clock.
CLK
Figure 1:
PLL and Clock
Dividers
The PLL's initial settings are determined by the state of any mode pins on the
xCORE-200 device. The standard configuration allows a 25MHz external clock to
be used to operate the xCORE tiles and the switch at 400MHz, and the reference
Publication Date: 2016/10/3
XMOS © 2016, All Rights Reserved
Divider Multiplier
Stage 1 Stage
÷(R+1) *((F+1)÷2)
Comparator
Freq
USB
Clk
Divider
Stage 2
÷(OD+1)
VCO System
Freq Freq
Switch
Divider
Reference
Divider
xCORE Tile
Divider
xCORE Tile
Divider
RGMII
Divider
Document Number: XM010761A
Switch
Clk
Ref
Clk
XCore0
Tile
Clk
XCore1
Tile
Clk
RGMII
TX Clk