Revisions following interval review 24/02/10 Revisions for power supply sequencing 02/03/10 Revisions for board release 1V1 27/04/10 Revisions for R102 28/05/10 Revisions for MIDI, PLL & XTAG2 29/06/10 Revisions for board release 1V2 www.xmos.com Downloaded from Elcodis.com electronic components distributor...
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 4/32 2 Introduction The USB Audio 2.0 Reference Design, XS1-L2 Edition (hereafter "the board") is a hardware reference design for a multi-channel USB audio interface using the XMOS XS1-L2 dual-core event-driven processor. It contains a single XS1-L2 device enabling implementation of a complete USB 2.0 high-speed device compliant with release 2.0...
Page 5
Integrated instrument and microphone pre-amplifier Integrated headphone amplifier on analogue outputs 1/2 Powered via USB bus or external 5V source XMOS XSYS debug header for easy programming/debug from the host using the XMOS XTAG2 debug adapter Eight LEDs for programmable use...
Page 6
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 6/32 2.2 Board Components The diagram below shows the layout of the main components of the board: XS1-L2 Device 1V0 Core Supply Audio CODEC 13MHz Oscillator Headphone Pre-Amp 4Mb SPI FLASH Instrument &...
Page 7
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 7/32 2.3 Connectors The diagram below shows the layout of the connectors on the board: 5V DC Power In Analogue 5/6 OUT (Stereo 3.5mm Jack) MIDI Input & Output (Via Gameport) Analogue 7/8 OUT (Stereo 3.5mm...
XSYS debug interface. 3.3 Boot The boot mode of the XS1-L2 is set by the MODE3 and MODE2 pins which are connected together on the board. With MODE3 and MODE2 both high (default), the device will boot from the 4Mb SPI FLASH on the board.
ULPI connection to XCore 0 of the XS1-L2. On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L2 is ready to begin USB activity. The USB transceiver reset pin is connected to port X0P1M of the XS1-L2 in order that it can be controlled by software.
Quad speed 100-200kHz The reset input to the CODEC is mapped to bit 3 of port X1P4A on the XS1-L2. The interrupt output from the CODEC is mapped to bit 3 of port X1P4B on the XS1-L2. 5.1 Analogue Audio I/O [4 - 12] 3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio inputs and...
Gameport connector. The signals are buffered using 5V line drivers and are then connected to 1-bit ports on the XS1-L2, via a 5V to 3.3V buffer. pull ups are placed on the MIDI IN signal from the connector and on the MIDI OUT signal from the XCore.
The source for the PLL is either the SYNC_OUT signal from the XS1-L2 or the word clock input as controlled by the SYNC_SEL signal. The SYNC_SEL signal is mapped to bit 0 of port X1P4A on the XS1-L2 as shown in the port map.
X0P1C X0P1D MOSI The XMOS development tools include the XFLASH utility for programming compiled programs into the flash memory via the XS1-L2. Software may also access the FLASH memory at run-time by interfacing with the above ports. www.xmos.com Downloaded from Elcodis.com...
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 14/32 11 XSYS Interface [18] A standard XMOS XSYS interface is provided to allow host debug of the board via JTAG. An XTAG2 USB debug adapter can be plugged into this port to allow running/debug- ging code, programming the FLASH memory via the XS1-L2 and selection of boot mode.
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 15/32 12 User LEDs [I] The board provides eight user LEDs that can be driven by software. These are marked on the board as LED 0 though to LED 7. The LEDs are connected to port X1P8B, the...
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 16/32 13 Expansion Header [17] The board provides a general purpose input/output expansion header to allow interfacing to custom boards. For example, this could be an I C display, eight LEDs and four buttons to make a user interface.
+5V VBus supply from the USB connector. The board will use approximately 300mA when fully configured and operating. The required core and IO voltages for the XS1-L2 are derived from 5V as follows: A low cost 1.5A buck switching regulator is used to generate the 1.0V core supply for the XS1-L2.
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 18/32 15 Printed Circuit Board The PCB is a 1.6mm four layer design in a XMOS XS1-G Development Kit form factor with dimensions of 180 x 120mm. It is made from FR4 ( r = 4.5) material and finished in immersion gold.
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 19/32 16 Test Points 16.1 Test Points by ID Test Point Port Signal +4V1A +3V3 +1V8 +1V0 OSC_13M PLL_WCLK VBUS TP10 X0P1J0 OPTICAL_RX TP11 X1P1N0 DAC_SD4 TP12 X1P1H0 DAC_SD3 TP13...
Page 20
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 20/32 16.2 Test Points by Signal 16.2.1 Power Signal Port Test Point +1V0 +1V8 +3V3 +4V1A NA VBUS 16.2.2 XS1-L2 System Signal Port Test Point OSC_13M PLL_LOCK X1P4B1 TP29 16.2.3 Audio Clocking...
Page 21
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 21/32 16.2.4 Codec Audio Signal Port Test Point ADC_SD1 X1P1G0 TP22 ADC_SD2 X1P1A0 TP21 ADC_SD3 X1P1B0 TP20 DAC_SD1 X1P1M0 TP14 DAC_SD2 X1P1F0 TP13 DAC_SD3 X1P1H0 TP12 DAC_SD4 X1P1N0 TP11 CODEC_LRCLK X1P1E0...
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 22/32 17 Port Map The table below provides a full description of the port to signal mappings used on the board. Port XCore P1A0 SPI_MISO ADC_SD2 P1B0 SPI_SS ADC_SD3 P4A0...
General tidy up and minor track changes. 19.2 Changes From 1V1 To 1V2 Added buffer for MIDI I/O to correct 5V going into XS1-L2 I/Os. Added pull ups on MIDI signals to stop startup glitches. Added 47pf cap to slow coax output and tidied up digital out layout.
“Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims.