XMOS xCORE-200 Multi-channel Audio board Design Manual page 28

USB Audio Design Guide
from the incoming master clock (typically the output of the external oscillator or
PLL). The audio driver is implemented in the file audio.xc .
The audio driver captures and plays audio data over I2S. It also forwards on relevant
audio data to the S/PDIF transmit core.
The audio core must be connected to a CODEC that supports I2S (other modes
such as "left justified" can be supported with firmware changes). In slave mode, the
XMOS device acts as the master generating the Bit Clock (BCLK) and Left-Right Clock
(LRCLK, also called Word Clock) signals. Any CODEC or DAC/ADC combination that
supports I2S and can be used.
Figure
and the CODEC.
Signal
LRCLK
BCLK
SDIN
Figure 12:
SDOUT
I2S Signals
MCLK
The bit clock controls the rate at which data is transmitted to and from the CODEC.
In the case where the XMOS device is the master, it divides the MCLK to generate
the required signals for both BCLK and LRCLK, with BCLK then being used to clock
data in (SDIN) and data out (SDOUT) of the CODEC.
Figure
rates (note that this reflects the single tile L-Series reference board configuration):
Sample Rate (kHz)
44.1
88.2
Figure 13:
176.4
Clock Divides
48
used in single
tile L-Series 96
Ref Design
192
The master clock must be supplied by an external source e.g. clock generator,
fixed oscillators, PLL etc to generate the two frequencies to support 44.1kHz and
48kHz audio frequencies (e.g. 11.2896/22.5792MHz and 12.288/24.576MHz
respectively). This master clock input is then provided to the CODEC and the XMOS
device.
XM0088546.1
12 shows the signals used to communicate audio between the XMOS device
Description
The word clock, transition at the start of a sample
The bit clock, clocks data in and out
Sample data in (from CODEC/ADC to the XMOS device)
Sample data out (from the XMOS device to CODEC/DAC)
The master clock running the CODEC/DAC/ADC
13 shows some example clock frequencies and divides for different sample
MCLK (MHz)
11.2896
11.2896
11.2896
24.576
24.576
24.576
BCLK (MHz) Divide
2.819 4
5.638 2
11.2896 1
3.072 8
6.144 4
12.288 2
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