Integra DTR-7.6 Series Service Manual page 60

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MICROPROCESSOR TERMINAL DESCRIPTIONS
No. Pin Name
1 Vref
2 AVcc
3 P97/~ADTRG/SIN4
4 P96/ANEX1/SOUT4
5 P95/ANEX0/CLK4
6 P94/DA1/TB4IN
7 P93/DA0/TB3IN
8 P92/TB2IN/SOUT3
9 P91/TB1IN/SIN3
10 P90/TB0IN/CLK3
11 P141
12 P140
13 BYTE
14 CNVSS
15 P87/XCIN
16 P86/XCOUT
17 ~RESET
18 XOUT
19 VSS
20 XIN
21 VCC1
22 P85/~NMI
23 P84/~INT2
24 P83/~INT1
25 P82/~INT0
26 P81/TA4IN/~U
27 P80/TA4OUT/U
28 P77/TA3IN
29 P76/TA3OUT
30 P75/TA2IN/~W
31 P74/TA2OUT/W
32 P73/~CTS2/~RTS2/TA1IN/~V
TE
L 13942296513
33 P72/CLK2/TA1OUT/V
34 P71/RXD2/SCL2/TA0IN/TB5IN
35 P70/TXD2/SDA2/TA0OUT
36 P67/TXD1/SDA1
37 Vcc1
38 P66/RXD1/SCL1
39 Vss
40 P65/CLK1
41
P64/~CTS1/~RTS1/~CTS0/CLKS1
42 P63/TXD0/SDA0
43 P62/RXD0/SCL0
44 P61/CLK0
45 P60/~CTS0/~RTS0
46 P137
47 P136
48 P135
49 P134
50 P57/~RDY/CLKOUT
51 P56/ALE
52 P55/~HOLD
53 P54/~HLDA
54 P133
55 P132
56 P131
57 P130
58 P53/BCLK
59 P52/~RD
60 P51/~WRH/~BHE
61 P50/~WRL/~WR
62 P127
63 P126
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64 P125
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Function I/O
Vref
AVcc
O
O
OSDSDO
O
OSDCLK
OSDCS O
XMRST O
XMSDO O
XMSDI I
XMCLK O
I
~XMREQ1
~XMREQ2 O
BYTE
CNVss
~SDET I
~SYNC I
~RESET I
Xout
Vss
Xin
Vcc1
~NMI I
I
~VSYNC
~REMIN I
POFF I
~ADCRST O
DIRINT I
~DIRCS O
~DIRRST O
~DSPFCS O
~DSPCS O
~VMUT O
VDM_SCK O
VDM_SI I
VDM_SO O
FTXD O
FRXD I
FCLK O
FBUSY O
PLLSDA/VCSDA I/O
PLLSCL/VCSCL O
~STEREO I
~TUNED I
~VDMRST O
VDM_STB I
TXMUTE O
RXMUTE I
~DSPINT I
~DSPFINT I
~DSPRST O
MLTSEL O
Z2VCLK O
Z2VDAT O
Z2VMUT O
VOLSTB O
VOLCLK O
VOLDAT O
~FCE I
~VCRST O
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Act. Description
A/D Reference Vltage (Vcc)
A/D Power supply
H No connect
H Data output for on-screen display.
CLK OSD IC Serial Communication Clock Output.
H OSD IC Chip Select Output
L Reset output to XM microprocessor.
H Serial data output to XM microprocessor.
H Serial data input from XM microprocessor.
CLK Serial clock output to XM microprocessor.
L Serial data chip request input from XM microprocessor.
H Serial data chip request output to XM microprocessor.
External bus width select pin. Connects to the ground.
Processor mode select pin. Connects to the ground via resistor.
L S Video input detection pin.
L Sync. detection pin.
L Reset input
Ceramic oscillator connection pin.
Power supply Ground
Ceramic oscillator connection pin.
Power supply Vcc.
L Connect the pull-up resistor.
L Vertical sync signal detection input.
L Remote control input.
H Power failure detection input pin.
L Multi channel AD Reset output
H DIR interrupt request detection pin.
L DIR/CODEC chip select output pin.
L DIR/CODEC reset output pin.
L Chip select output pin for DSP AB
L Chip select output pin for DSP C
Q Q
L Video mute control output pin
3 6 7 1 3 1 5
H Clock output pin to Video microprocessor.
H Data output pin to Video microprocessor.
H Data input pin from Video microprocessor.
H Port for writing Flash./RS232 port output.
Power supply
H Port for writing Flash./RS232 port input.
Ground
CLK Port for writing Flash.
H Port for writing Flash.
H Tuner I2C bus data pin/Video Dec/Enc serial communication data output pin
CLK Tuner I2C bus clock output pin/Video Dec/Enc serial communication clock output pin
L FM stereo broadcast defection input
L Tuner tuned detection input pin
H Reset output pin to video microprocessor.
H Strobe input pin from video microprocessor.
H Muting output pin to video microprocessor.
H Muting input pin from video microprocessor.
L Interrupt request detection pin for DSP C.
L Interrupt request detection pin for DSP AB.
Connect to the ground.
L DSP reset output pin
H Multi Ch AD and HDMI(I2S) select pin
H Serial clock output pin for Zone2 Volume IC.
H Serial data output pin for Zone2 Volume IC.
H Mute control output pin for Zone2 Volume IC.
H Strobe output for Volume
CLK Serial clock output for Volume
H Serial data output for Volume
H Port for writing Flash.
L Video Dec/Enc reset control pin
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DTR-7.6
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