Integra DTR-7.6 Series Service Manual page 36

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
CS42528 (8-Ch Codec with S/PDIF Receiver)
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
MUTEC
FILT+
VQ Ref
REFGND
VA
AGND
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
TE
L 13942296513
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
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TXP VARX AGND LPFLT
Clock/Data
Rx
Recovery
GPO
MUTE
ADC#1 Digital Filter
ADC#2 Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
CX_SDIN1 1
CX_SCLK 2
CX_LRCK 3
VD 4
DGND 5
VLC 6
SCL/CCLK
7
SDA/CDOUT
8
AD1/CDIN 9
AD0/CS 10
INT 11
RST 12
AINR- 13
AINR+ 14
AINL+ 15
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AINL-
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2 9
8
DGND DGND VD
C&U Bit
Data Buffer
S/P DIF
Decoder
Format
Detector
Internal MCLK
DEM
Gain & Chip
ADC
Serial
Data
Gain & Chip
Q Q
3 6 7 1 3 1 5
CS42528
co
.
9 4 2 8
VD
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
RMCK
Mult/Div
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CODEC
Serial
CX_SDIN4
Port
0 5 8 2 9 9 4 2 8
BLOCK DIAGRAM
48
RXP1/GPO1
47 RXP2/GPO2
46 RXP3/GPO3
45 RXP4/GPO4
44 RXP5/GPO5
43 RXP6/GPO6
42 RXP7/GPO7
41 VARX
40
AGND
39 LPFLT
38 MUTEC
37 AOUTA1-
36 AOUTA1+
m
35 AOUTB1+
34 AOUTB1-
33 AOUTA2-
PIN LAYOUT
DTR-7.6
9 9
9 9