Integra DTR-7.6 Series Service Manual page 35

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
BR24L02FV-W/08FV-W(256X8 bit EEPROM)
1
A0
2
A1
3
A2
High-voltage
4
GND
generation circuit
TE
L 13942296513
A0,A1,A2
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2k Bit EEPROM Array
8bit
Address
Slave word
8bit
Decorder address register
START
Control circuit
Power voltage
detection
I/O
Terminal
-
Vcc
-
GND
I
I
SCL
I/O
SDA
I
WP
x ao
y
i
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8
8bit
Data
register
STOP
ACK
Function
Apply a power source.
Ground termional
Q Q
3 6 7 1 3
Slave address setting terminal
Serial clock input
Slave and word address.
Serial data input and output
Write protect terminal
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2 9 9 4 2 8
8
Vcc
7 WP
6
SCL
5 SDA
1 5 0 5 8 2 9 9 4
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co
DTR-7.6
9 9
2 8 9 9