Integra DTR-7.6 Series Service Manual page 56

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
SiI9031(HDMI PanelLink Cinema Receiver)
Pin #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
TE
L 13942296513
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
www
140
141
142
143
144
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Pin Name I/O Description
DGND ACR PLL GND
DVCC18 ACR PLL VCC (1.8V)
IOGND Input/Output Pin GND
IOVCC Input/Output Pin VCC (3.3V)
MUTEOUT O Mute Audio Output
SPDIF O S/PDIF Audio Output
CVCC18 Digital Logic VCC (1.8V)
CGND Digital Logic GND
SD3 O I2S Serial Data Output
SD2 O I2S Serial Data Output
SD1 O I2S Serial Data Output
SD0 O I2S Serial Data Output
WS O I2S Word Select Output
WCK O I2S Serial Clock Output
MCLKIN I Audio Master Clock Input Reference
MCLKOUT O Audio Master Clock Output
IOVCC Input/Output Pin VCC (3.3V)
IOGND Input/Output Pin GND
CGND Digital Logic GND
CVCC18 Digital Logic VCC (1.8V)
NC No connect.
AUDPVCC18 ACR PLL VCC (1.8V)
AUDPGND ACR PLL GND
XTALOUT O Crystal Clock Output
XTALIN I Crystal Clock Input
XTALVCC ACR PLL Crystal Input VCC
REGVCC ACR PLL Regulator VCC
NC No connect.
RSVDL I Reversed, must be tied LOW.
RESET I Reset pin Active Low.
SCDT O Indicates active video at HDMI input port.
INT O Interrupt Output.
CVCC18 Digital Logic VCC (1.8V)
CGND Digital Logic GND
CLK48B I/O Data Bus latch enable
IOGND Input/Output Pin GND
IOVCC Input/Output Pin VCC (3.3V)
Q23 O 24-bit Output Pixel Data Bus.
Q22 O 24-bit Output Pixel Data Bus.
Q21 O 24-bit Output Pixel Data Bus.
Q20 O 24-bit Output Pixel Data Bus.
CVCC18 Digital Logic VCC (1.8V)
CGND Digital Logic GND
Q19 O 24-bit Output Pixel Data Bus.
Q18 O 24-bit Output Pixel Data Bus.
Q17 O 24-bit Output Pixel Data Bus.
Q16 O 24-bit Output Pixel Data Bus.
IOGND Input/Output Pin GND
ODCK O Output Data Clock
IOVCC Input/Output Pin VCC (3.3V)
Q15 O 24-bit Output Pixel Data Bus.
Q14 O 24-bit Output Pixel Data Bus.
Q13 O 24-bit Output Pixel Data Bus.
Q12 O 24-bit Output Pixel Data Bus.
CGND Digital Logic GND
CVCC18 Digital Logic VCC (1.8V)
Q11 O 24-bit Output Pixel Data Bus.
Q10 O 24-bit Output Pixel Data Bus.
Q9 O 24-bit Output Pixel Data Bus.
Q8 O 24-bit Output Pixel Data Bus.
Q7 O 24-bit Output Pixel Data Bus.
IOVCC Input/Output Pin VCC (3.3V)
IOGND Input/Output Pin GND
Q6 O 24-bit Output Pixel Data Bus.
Q5 O 24-bit Output Pixel Data Bus.
CGND Digital Logic GND
CVCC18 Digital Logic VCC (1.8V)
Q4 O 24-bit Output Pixel Data Bus.
Q3 O 24-bit Output Pixel Data Bus.
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Q2 O 24-bit Output Pixel Data Bus.
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Q1 O 24-bit Output Pixel Data Bus.
Q0 O 24-bit Output Pixel Data Bus.
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2 9
8
Q Q
3 6 7 1 3 1 5
co
.
9 4 2 8
Use
Ground
Power
Ground
Power
Digital Audio
Digital Audio
Power
Ground
Digital Audio
Digital Audio
Digital Audio
Digital Audio
Digital Audio
Digital Audio
Digital Audio
Digital Audio
Power
Ground
Ground
Power
Configuration/Programming
Power
Ground
Digital Audio
Digital Audio
Power
Power
Configuration/Programming
Configuration/Programming
Configuration/Programming
Configuration/Programming
Configuration/Programming
Power
0 5 8 2 9 9 4 2 8
Ground
Configuration/Programming
Ground
Power
Digital Video
Digital Video
Digital Video
Digital Video
Power
Ground
Digital Video
Digital Video
Digital Video
Digital Video
Ground
Digital Video
Power
Digital Video
Digital Video
Digital Video
Digital Video
Ground
Power
Digital Video
Digital Video
Digital Video
Digital Video
Digital Video
Power
Ground
Digital Video
Digital Video
Ground
Power
m
Digital Video
Digital Video
Digital Video
Digital Video
Digital Video
DTR-7.6
9 9
9 9