Integra DTR-7.6 Series Service Manual page 30

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183 (Advanced Video Decoder with 10-Bit ADC and Component Support)
BLOCK DIAGRAM
ADV7183
ISO
REFOUT
AIN1
ANALOG I/P
AIN2
MULTIPLEXING
AUTOMATIC
AIN3
GAIN
CONTROL
(AGC)
AIN4
CLAMP AND
AIN5
DC RESTRE
AIN6
PWRDN
TE
L 13942296513
TERMINAL DESCRIPTION
Pin
1
2
3, 14
4, 15
5-8, 19-24,
32, 33, 73-76
9, 31, 71
10, 30, 72
11
12
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13
.
16
17, 18, 34, 35 GPO[3:0]
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SHAPING
AND
NOTCH LPF
LUMA
10-BIT
ANTIALIAS
ADC
LPF
27MHz
10-BIT
SWITCH
ADC
VIDEO TIMING AND
CONTROL BLOCK
HSYNC FIELD VSYNC HREF
Mnemonic Input/Output
VS/VACTIVE O VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
HS/HACTIVE O
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
DVSSIO G Digital I/O Ground
DVDDIO P Digital I/O Supply Voltage (3.3 V)
P15-P0 O Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15-P8),
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
DVSS1-3 G Ground for Digital Supply
DVDD1-3 P Digital Supply Voltage (3.3 V)
AFF O Almost Full Flag. A FIFO control signal indicating when the FIFO has
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
HFF/QCLK/GL I/O Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
x AEF ao O Almost Empty Flag. A FIFO control signal, it indicates when the FIFO u163
y
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
i
CLKIN I Asynchronous FIFO Clock. This asynchronous clock is used to output
data onto the P19-P0 bus and other control signals.
O General-Purpose Outputs controlled via I C
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2 9
8
RESAMPLING
PEAKING
AND
HPF/LPF HORIZONTAL
SCALING
SYNC
DETECTION
RESAMPLING
SUB-
AND
CARRIER
RECOVERY HORIZONTAL
DTO SCALING
CHROMA
SHAPING
ANTIALIAS
LPF
LPF
27MHz XTAL
OSCILLATOR
BLOCK
VREF CLOCK CLOCK RESET
Q Q
3 6 7 1 3
Function
.
2
9 4 2 8
P15-P0
PIXEL
O/P POR T
LUMA
DELAY
BLOCK
FIFO CONTROL
BLOCK
AND
2H LINE
PIXEL
MEMORY
OUTPUT
FORMATTER
CHROMA
COMB
FILTER
LLC
SYNTHESIS
WITH LINE-
LOCKED
OUTPUT
CLOCK
I 2 C-COMPATIBLE
INTERFACE PORT
SDATA SCLOCK ALSB
1 5 0 5 8 2 9 9 4
m
co
DTR-7.6
9 9
AFF
HFF/QCLK
AEF
DV
RD
OE
GL/CLKIN
LLC1
LLC2
LLCREF
ELPF
2 8 9 9