Integra DTR-7.6 Series Service Manual page 33

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
AK4384(106dB 192kHz 24-Bit 2ch
P/S
SMUTE/CSN
µP
ACKS/CCLK
Interface
DIF0/CDTI
LRCK
Audio
Data
BICK
Interface
SDTI
No.
1
TE
L 13942296513
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Note: All input pins except pull-up pin should not be left floating.
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∆ Σ
De-emphasis
Control
8X
ATT
Interpolator
8X
ATT
Interpolator
PDN
Pin Name I/O Function
MCLK I Master Clock Input Pin
BICK I Audio Serial Data Clock Pin
SDTI I Audio Serial Data Input Pin
LRCK I L/R Clock Pin
PDN I Power-Down Mode Pin
SMUTE I Soft Mute Pin in parallel mode
CSN I Chip Select Pin in serial mode
ACKS I Auto Setting Mode Pin in parallel mode
CCLK I Control Data Clock Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode
CDTI I Control Data Input Pin in serial mode
P/S I
Parallel/Serial Select Pin
AOUTR O Rch Analog Output Pin
AOUTL O Lch Analog Output Pin
VCOM O Common Voltage Pin, VDD/2
VSS - Ground Pin
VDD - Power Supply Pin
DZFR O Rch Data Zero Input Detect Pin
DZFL O Lch Data Zero Input Detect Pin
x ao
y
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8
DAC)
MCLK
VDD
VSS
Clock
Divider
VCOM
DZFL
DZFR
∆Σ
SCF
AOUTL
Modulator LPF
∆Σ
SCF
AOUTR
Modulator LPF
Q Q
3 6 7 1 3
An external TTL clock should be input on this pin.
When at "L", the AK4384 is in the power-down mode and is held in reset. The
AK4384 should always be reset upon power-up.
"H": Enable, "L": Disable
"L": Manual Setting Mode, "H": Auto Setting Mode
"L": Serial control mode, "H": Parallel control mode
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
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2 9 9 4 2 8
1
2
3
4
5
6
7
8
Pin Layout
1 5 0 5 8 2 9 9 4
(Internal pull-up pin)
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co
DTR-7.6
9 9
16
15
14
13
12
11
10
9
2 8 9 9