Integra DTR-7.6 Series Service Manual page 48

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
MX26LV040-70/EN29LV040A(4M-bit CMOS High Speed Flash Memory)
BLOCK DIAGRAM
A0~A18
TE
L 13942296513
BLOCK DIAGRAM
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE
8
Vcc
9
A18
10
A16
11
A15
12
A12
www
13
A7
14
A6
15
A5
16
A4
.
http://www.xiaoyu163.com
CONTROL
WE
INPUT
OE
LOGIC
CE
ADDRESS
LATCH
AND
BUFFER
Q0-Q7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
x ao u163
y
18
17
i
http://www.xiaoyu163.com
2 9
8
PROGRAM/ERASE
HIGH VOLTAGE
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
PGM
SENSE
DATA
Q Q
AMPLIFIER
3 6 7 1 3
HV
PROGRAM
DATA LATCH
I/O BUFFER
PIN DESCRIPTION
SYMBOL PIN NAME
OE
A0~A18 Address Input
A10
CE
Q0~Q7 Data Input/Output
Q7
CE Chip Enable Input
Q6
WE Write Enable Input
Q5
OE Output Enable Input
Q4
VCC Power Supply Pin (+5V)
Q3
GND Ground Pin
GND
Q2
Q1
Q0
A0
A1
A2
A3
.
9 4 2 8
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
1 5 0 5 8 2 9 9 4
COMMAND
DATA LATCH
m
co
DTR-7.6
9 9
2 8 9 9