Siemens SINUMERIK 880 SW 6 Planning Manual page 168

01.93
The PARAMETER TEST signals for OB 1 to OB 7 allow the parameters to be checked
exclusively for possible changes. This restricted parameter test reduces the processing time of
a block during normal operation.
Example:
:
AN F 4.1
JC=FORT
:
Test routine
:
ADDRESSING ERROR RECOGNITION
1 signal: Addressing error recognition selected.
0 signal: Addressing error recognition not selected.
Note:
Addressing error recognition can be switched in function blocks with the S-5 commands RAE
and IAE.
SEGMENT OVERRANGE WITH BLOCKS
1 signal: Segment overrange with blocks permitted.
0 signal: Segment overrange with blocks not permitted.
Since a block can be located outside the segment limits from SW 6 onwards, not only the
offset address but also the segment number has to be taken into account with absolute
address calculation.
PLC OPERATION (PLC I, PLC II)
Bit 0=1: PLC I selected (programmer in on-line mode or PLC status of the NC).
Bit 1=1: PLC II selected (programmer in on-line mode or PLC status of the NC).
PROCESSING DELAY (OB 2 to OB 7)
1 signal: Processing delay effected by the relevant OB.
0 signal: No meaning.
Note:
If time or process-alarm controlled program execution is called again before it has been
completed, the system program sets the relevant PROCESSING DELAY bit (depending on
PLC MD 6048 for PLC I). These bits are reset with a cold or warm restart. When the bit is
set the corresponding event counter processing delay in the diagnostics DB (DW 1, DW 22
to DW 27) is incremented by one
–––––––
1) If using a SIMATIC S5-155U, refer to SINUMERIK 880 with S5-155U, Difference Description to PLC 135 WB in
this context.
d) with GA2, software version 1 and higher
© Siemens AG 1991 All Rights Reserved
SINUMERIK 880 (PJ)
5 Description of Basic Signals (FY 0 ... FY 24)
1)
d)
.
6ZB5 410-0HE02
5.1 PLC auxiliary signals
FY 5, bit 7
FY 5, bit 6
FY 5, bit 0 and 1
FY 6, bit 2 to 7
5–5