Denon S-5BD Service Manual page 141

Pin Pin Name Symbol
DSPPWR/
88 P106/(AN6)
SubnCONFIG
DSP ROMRST/
89 P105/(AN5)
SUBnCE
90 P104/(AN4) NC
DSPFLAG0/
91 P103/(AN3)
SUBDATA_O
DSP1ICS/
92 P102/(AN2)
SUBnCS
DSPFLAG1/
93 P101/(AN1)
SUBASDI
94 AVSS AVSS
95 P100/(AN0) VSEL CLK
96 VREF VREF
97 AVCC AVCC
98 P97/(SIN4) Tx EN
(DSP2ICS)/
99 P96/(SOUT4) (O)/I
SCONF_DONE
100 P95/(CLK4) NC
Op Pu/Pd
I/O Type Det
(Int.) (Ext.)
O/O C - - -
O/O C - - -
O - Lv - SCPU3VPu
I/O - Lv - Pd
O/O C - D3VPu
I/O C - D3VPu
- - - - -
O C - - -
- - - - -
- - - - -
O C - - -
- - - Pd
O C - - -
PURE CEC
Res P.OFF Q.STBY
D STBY
Z Z O/L O/L O/L
Z Z O/L O/L O/L
Z Z - - -
Z Z - - -
Z Z O/L O/L O/L
Z Z O/L O/L O/L
- - - - -
Z Z O/L O/L O/L
- - - - -
- - - - -
Z Z O/L - -
Z Z O/L O/L O/L
Z Z O/L O/L O/L
141
CEC +
Function
Q STBY
DSP control pin (ADSP-21367-333) /FPGA rewriting (For
O/L
GUI FPGA: NCONF)
Rewriting memory reset (Reset : L)/FPGA rewriting control
O/L
(For GUI FPGA: CE)
- Non
DSP control pin (ADSP-21367-333): Confirming the
- operation/FPGA rewriting control (For GUI FPGA: Data
light)
DSP control pin (ADSP-21367-333): Communicating
O/L
enable/FPGA rewriting control (For GUI FPGA: CS)
DSP control pin (ADSP-21367-333) /FPGA rewriting
O/L
control (For GUI FPGA: Communication response)
- AD GND
O/L GUI built-in VIDEO SW cotrol pin
- AD 3.3 standard +V
- AD +3.3V
- AD8195 ENABLE pin for Front HDMI control
Reserve (DSP1 control pin (ADSP-21367-333):
O/L Communicate enable)/FPGA rewriting control (For GUI
FPGA: ASDI)
O/L Non