NXP MKL04Z16VLF4 Manuals

Manuals and User Guides for NXP MKL04Z16VLF4. We have 1 NXP MKL04Z16VLF4 manual available for free PDF download: Reference Manual

NXP Semiconductors MKL04Z16VLF4 Reference Manual

NXP Semiconductors MKL04Z16VLF4 Reference Manual (658 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 7 MB

Table of Contents

Table of Contents
3
Chapter 1 About this Document

29
- Overview
  29
  - Purpose
    29
  - Audience
    29
- Conventions
  29
  - Numbering Systems
    29
  - Typographic Notation
    30
  - Special Terms
    30
Chapter 2 Introduction

31
- Overview
  31
- Kinetis L Series
  31
- KL04 Sub-Family Introduction
  34
- Module Functional Categories
  35
  - ARM® Cortex™-M0+ Core Modules
    35
  - System Modules
    36
  - Memories and Memory Interfaces
    37
  - Clocks
    37
  - Security and Integrity Modules
    37
  - Analog Modules
    38
  - Timer Modules
    38
  - Communication Interfaces
    39
  - Human-Machine Interfaces
    39
- Orderable Part Numbers
  39
Chapter 3 Chip Configuration

41
- Introduction
  41
- Module to Module Interconnects
  41
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    42
  - Analog Reference Options
    43
- Core Modules
  44
- System Modules
  51
- Clock Modules
  64
  - MCG Configuration
    64
  - OSC Configuration
    65
- Memories and Memory Interfaces
  66
- Analog
  71
  - 12-Bit SAR ADC Configuration
    71
  - CMP Configuration
    75
- Timers
  77
  - Timer/Pwm Module Configuration
    77
  - PIT Configuration
    79
  - Low-Power Timer Configuration
    81
  - RTC Configuration
    82
- Communication Interfaces
  84
  - SPI Configuration
    84
  - I2C Configuration
    85
  - UART Configuration
    85
- Human-Machine Interfaces (HMI)
  87
  - GPIO Configuration
    87
- Memory Map
  88
- Introduction
  91
- System Memory Map
  91
- Flash Memory Map
  92
Chapter 4 Alternate Non-Volatile IRC User Trim Description

93
Chapter 5 Clock Distribution

101
- Introduction
  101
- Programming Model
  101
- High-Level Device Clocking Diagram
  101
- Clock Definitions
  102
  - Device Clock Summary
    103
- Internal Clocking Requirements
  105
  - Clock Divider Values after Reset
    105
  - VLPR Mode Clocking
    106
- Clock Gating
  106
- Module Clocks
  106
  - PMC 1-Khz LPO Clock
    107
  - COP Clocking
    108
  - RTC Clocking
    108
  - LPTMR Clocking
    109
  - TPM Clocking
    109
  - UART Clocking
    110
Chapter 6 Reset and Boot

111
- Introduction
  111
- Reset
  111
  - Power-On Reset (POR)
    112
  - System Reset Sources
    112
  - MCU Resets
    115
  - Reset Pin
    116
  - Debug Resets
    117
- Boot
  118
  - Boot Sources
    118
  - FOPT Boot Options
    118
  - Boot Sequence
    119
Chapter 7 Power Management

121
- Introduction
  121
- Clocking Modes
  121
  - Partial Stop
    121
  - DMA Wakeup
    122
  - Compute Operation
    123
  - Peripheral Doze
    124
  - Clock Gating
    125
- Power Modes
  125
- Entering and Exiting Power Modes
  127
- Module Operation in Low Power Modes
  127
Chapter 8 Security

131
- Introduction
  131
- Flash Security
  131
- Security Interactions with Other Modules
  131
  - Security Interactions with Debug
    132
Chapter 9 Debug

133
- Introduction
  133
- Debug Port Pin Descriptions
  133
- SWD Status and Control Registers
  134
  - MDM-AP Control Register
    135
  - MDM-AP Status Register
    136
- Debug Resets
  138
- Micro Trace Buffer (MTB)
  139
- Debug in Low Power Modes
  139
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    140
  - Introduction
    141
Chapter 10

142
- Port Control and Interrupt Module Features
  142
- Clock Gating
  143
- KL04 Pinouts
  145
- Module Signal Description Tables
  149
  - System Modules
    150
  - Analog
    151
  - Communication Interfaces
    152
  - Introduction
    153
  - Modes of Operation
    154
Chapter 32

155
- Detailed Signal Description
  155
- KL04 Sub-Family Reference Manual, Rev. 3.1, November
  156
- Pin Control Register N (Portx_Pcrn)
  158
- Global Pin Control Low Register (Portx_Gpclr)
  160
- Global Pin Control High Register (Portx_Gpchr)
  161
- Functional Description
  162
- Global Pin Control
  163
- Introduction
  165
Chapter 12

167
Chapter 13

193
- Power Mode Control Register (SMC_PMCTRL)
  193
- Stop Control Register (SMC_STOPCTRL)
  194
- Power Mode Status Register (SMC_PMSTAT)
  195
- Functional Description
  196
- Power Mode Entry/Exit Sequencing
  199
- Run Modes
  201
- Wait Modes
  203
- Stop Modes
  204
- Debug in Low Power Modes
  207
- Introduction
  209
Chapter 14

210
Chapter 15 LLWU Signal Descriptions

220
- LLWU Pin Enable 1 Register (LLWU_PE1)
  221
- LLWU Pin Enable 2 Register (LLWU_PE2)
  222
- LLWU Module Enable Register (LLWU_ME)
  223
- LLWU Flag 1 Register (LLWU_F1)
  225
- LLWU Flag 3 Register (LLWU_F3)
  226
- LLWU Pin Filter 1 Register (LLWU_FILT1)
  228
- LLWU Pin Filter 2 Register (LLWU_FILT2)
  229
- Functional Description
  230
- LLS Mode
  231
  - Introduction
    233
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    234
- System Reset Status Register 1 (RCM_SRS1)
  235
  - Reset Pin Filter Control Register (RCM_RPFC)
    236
  - Reset Pin Filter Width Register (RCM_RPFW)
    237
  - Introduction
    239
  - Overview
    240
  - Modes of Operation
    241
  - Memory Map and Register Definition
    242
Chapter 17

255
- Additional Details on Decorated Addresses and GPIO Accesses
  255
  - Application Information
    256
  - Introduction
    259
Chapter 18

260
- Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  260
- Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  261
  - Compute Operation Control Register (MCM_CPO)
    264
  - Introduction
    267
  - Features
    270
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    271
  - Memory Map and Register Definition
    272
- MTB_DWT Memory Map
  285
  - Introduction
    301
  - Functional Description
    302
Chapter 20 Arbitration

303
- Initialization/Application Information
  304
- Introduction
  305
- General Operation
  306
  - Introduction
    307
  - Features
    308
  - External Signal Description
    309
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    310
- DMA Channels with Periodic Triggering Capability
  311
- Freescale Semiconductor, Inc
  312
- DMA Channels with no Triggering Capability
  313
  - Initialization/Application Information
    314
  - Freescale Semiconductor, Inc
    315
  - Freescale Semiconductor, Inc
    316
  - Freescale Semiconductor, Inc
    317
  - Freescale Semiconductor, Inc
    318
  - Introduction
    319
Chapter 33

320
- Features
  320
- DMA Transfer Overview
  321
- Memory Map and Registers
  322
Chapter 23

323
- Source Address Register (Dma_Sarn)
  323
- Destination Address Register (Dma_Darn)
  324
- DMA Status Register / Byte Count Register (Dma_Dsr_Bcrn)
  325
- Freescale Semiconductor, Inc
  326
- DMA Control Register (Dma_Dcrn)
  327
  - Freescale Semiconductor, Inc
    328
  - Freescale Semiconductor, Inc
    329
  - Freescale Semiconductor, Inc
    330
  - Functional Description
    331
- Channel Initialization and Startup
  332
- Dual-Address Data Transfer Mode
  333
- Advanced Data Transfer Controls: Auto-Alignment
  334
- Termination
  335
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    336
  - Introduction
    337
  - Freescale Semiconductor, Inc
    338
  - Freescale Semiconductor, Inc
    339
  - Modes of Operation
    340
  - Freescale Semiconductor, Inc
    341
Chapter 24

342
- MCG Control 2 Register (MCG_C2)
  342
- MCG Control 3 Register (MCG_C3)
  343
- Freescale Semiconductor, Inc
  344
- MCG Control 6 Register (MCG_C6)
  345
- MCG Status and Control Register (MCG_SC)
  346
- Freescale Semiconductor, Inc
  347
- MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  348
  - Freescale Semiconductor, Inc
    349
  - Freescale Semiconductor, Inc
    350
  - Freescale Semiconductor, Inc
    351
- Low Power Bit Usage
  352
- External Reference Clock
  353
- Freescale Semiconductor, Inc
  354
- Initialization / Application Information
  355
  - Freescale Semiconductor, Inc
    356
  - Using a 32.768 Khz Reference
    357
    
    KL04 Sub-Family Reference Manual, Rev. 3.1, November
    358
    
    Freescale Semiconductor, Inc
    359
    
    Freescale Semiconductor, Inc
    360
    
    Freescale Semiconductor, Inc
    361
    
    Freescale Semiconductor, Inc
    362
    
    Freescale Semiconductor, Inc
    363
    
    Freescale Semiconductor, Inc
    364
    
    Introduction
    365
Chapter 28

366
- Block Diagram
  366
Chapter 25

367
- External Crystal / Resonator Connections
  367
- External Clock Connections
  368
  - Memory Map/Register Definitions
    369
  - Functional Description
    370
  - Freescale Semiconductor, Inc
    371
  - OSC Module Modes
    372
  - Counter
    373
    
    Reset
    374
    
    Introduction
    375
    
    Modes of Operation
    376
    
    KL04 Sub-Family Reference Manual, Rev. 3.1, November
    377
    
    Freescale Semiconductor, Inc
    378
    
    Introduction
    379
Chapter 22 Features

380
Chapter 27

381
- Glossary
  381
- External Signal Description
  382
  - Flash Configuration Field Description
    383
  - Register Descriptions
    384
    
    Freescale Semiconductor, Inc
    385
    
    Freescale Semiconductor, Inc
    386
    
    Freescale Semiconductor, Inc
    387
    
    Freescale Semiconductor, Inc
    388
    
    Freescale Semiconductor, Inc
    389
    
    Freescale Semiconductor, Inc
    390
    
    Freescale Semiconductor, Inc
    391
    
    Functional Description
    392
  - Flash Protection
    393
  - Flash Operation in Low-Power Modes
    394
  - Flash Reads and Ignored Writes
    395
    
    Freescale Semiconductor, Inc
    396
    
    Freescale Semiconductor, Inc
    397
    
    Freescale Semiconductor, Inc
    398
    
    Freescale Semiconductor, Inc
    399
  - Margin Read Commands
    400
  - Flash Command Description
    401
    
    Freescale Semiconductor, Inc
    402
    
    Freescale Semiconductor, Inc
    403
    
    Freescale Semiconductor, Inc
    404
    
    Freescale Semiconductor, Inc
    405
    
    Freescale Semiconductor, Inc
    406
    
    Freescale Semiconductor, Inc
    407
    
    Freescale Semiconductor, Inc
    408
    
    Freescale Semiconductor, Inc
    409
    
    Freescale Semiconductor, Inc
    410
    
    Freescale Semiconductor, Inc
    411
    
    Freescale Semiconductor, Inc
    412
    
    Freescale Semiconductor, Inc
    413
  - Security
    414
  - Freescale Semiconductor, Inc
    415
  - Reset Sequence
    416
  - Introduction
    417
  - Block Diagram
    418
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    419
  - Voltage Reference Select
    420
  - Analog Channel Inputs (Adx)
    421
  - ADC Status and Control Registers 1 (Adcx_Sc1N)
    422
    
    Freescale Semiconductor, Inc
    423
    
    Freescale Semiconductor, Inc
    424
  - ADC Configuration Register 1 (Adcx_Cfg1)
    425
  - Freescale Semiconductor, Inc
    426
  - ADC Configuration Register 2 (Adcx_Cfg2)
    427
  - ADC Data Result Register (Adcx_Rn)
    428
  - Compare Value Registers (Adcx_Cvn)
    429
  - Status and Control Register 2 (Adcx_Sc2)
    430
  - Freescale Semiconductor, Inc
    431
  - Status and Control Register 3 (Adcx_Sc3)
    432
  - ADC Offset Correction Register (Adcx_Ofs)
    433
  - ADC Plus-Side Gain Register (Adcx_Pg)
    434
  - ADC Plus-Side General Calibration Value Register (Adcx_Clps)
    435
  - ADC Plus-Side General Calibration Value Register (Adcx_Clp3)
    436
  - ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
    437
  - Functional Description
    438
  - Voltage Reference Selection
    439
  - Conversion Control
    440
    
    Freescale Semiconductor, Inc
    441
    
    Freescale Semiconductor, Inc
    442
    
    Freescale Semiconductor, Inc
    443
    
    Freescale Semiconductor, Inc
    444
    
    Freescale Semiconductor, Inc
    445
    
    Freescale Semiconductor, Inc
    446
  - Automatic Compare Function
    447
  - Freescale Semiconductor, Inc
    448
  - Calibration Function
    449
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    450
  - Temperature Sensor
    451
  - MCU Wait Mode Operation
    452
  - MCU Low-Power Stop Mode Operation
    453
- Initialization Information
  454
- Freescale Semiconductor, Inc
  455
- Application Information
  456
  - Freescale Semiconductor, Inc
    457
  - Sources of Error
    458
    
    Freescale Semiconductor, Inc
    459
    
    Freescale Semiconductor, Inc
    460
    
    Freescale Semiconductor, Inc
    461
    
    Freescale Semiconductor, Inc
    462
- Introduction
  463
Chapter 29

464
- Bit DAC Key Features
  464
- ANMUX Key Features
  465
- CMP Block Diagram
  466
- Freescale Semiconductor, Inc
  467
- Memory Map/Register Definitions
  468
- Functional Description
  474
  - Freescale Semiconductor, Inc
    475
  - Freescale Semiconductor, Inc
    476
- Freescale Semiconductor, Inc
  477
  - Freescale Semiconductor, Inc
    478
  - Freescale Semiconductor, Inc
    479
  - Freescale Semiconductor, Inc
    480
  - Freescale Semiconductor, Inc
    481
  - Freescale Semiconductor, Inc
    482
  - Power Modes
    483
  - Startup and Operation
    484
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    485
  - Freescale Semiconductor, Inc
    486
- CMP Interrupts
  487
- Digital-To-Analog Converter
  488
  - Voltage Reference Source Select
    489
  - Freescale Semiconductor, Inc
    490
Chapter 21 Introduction

491
- Modes of Operation
  492
Chapter 30 TPM Signal Descriptions

493
- TPM_EXTCLK — TPM External Clock
  494
- Freescale Semiconductor, Inc
  495
- Status and Control (Tpmx_Sc)
  496
- Counter (Tpmx_Cnt)
  497
- Modulo (Tpmx_Mod)
  498
- Channel (N) Status and Control (Tpmx_Cnsc)
  499
- Freescale Semiconductor, Inc
  500
- Channel (N) Value (Tpmx_Cnv)
  501
- Freescale Semiconductor, Inc
  502
- Configuration (Tpmx_Conf)
  503
- KL04 Sub-Family Reference Manual, Rev. 3.1, November
  504
- Functional Description
  505
  - Prescaler
    506
  - Freescale Semiconductor, Inc
    507
  - Input Capture Mode
    508
  - Output Compare Mode
    509
  - Freescale Semiconductor, Inc
    510
  - Edge-Aligned PWM (EPWM) Mode
    511
  - Center-Aligned PWM (CPWM) Mode
    512
  - Freescale Semiconductor, Inc
    513
  - Registers Updated from Write Buffers
    514
  - Reset Overview
    515
  - Freescale Semiconductor, Inc
    516
- Introduction
  517
Chapter 37

518
- Features
  518
Chapter 31 Memory Map/Register Description

519
- Freescale Semiconductor, Inc
  520
- PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  521
- Timer Load Value Register (Pit_Ldvaln)
  522
- Timer Control Register (Pit_Tctrln)
  523
- Timer Flag Register (Pit_Tflgn)
  524
- Freescale Semiconductor, Inc
  525
- Interrupts
  526
- KL04 Sub-Family Reference Manual, Rev. 3.1, November
  527
- Example Configuration for the Lifetime Timer
  528
  - Freescale Semiconductor, Inc
    529
  - Freescale Semiconductor, Inc
    530
  - Introduction
    531
- LPTMR Signal Descriptions
  532
  - Low Power Timer Control Status Register (Lptmrx_Csr)
    533
  - Low Power Timer Prescale Register (Lptmrx_Psr)
    534
  - Freescale Semiconductor, Inc
    535
  - Low Power Timer Compare Register (Lptmrx_Cmr)
    536
    
    Functional Description
    537
    
    Freescale Semiconductor, Inc
    538
  - LPTMR Compare
    539
  - LPTMR Hardware Trigger
    540
    
    Introduction
    541
    
    KL04 Sub-Family Reference Manual, Rev. 3.1, November
    542
  - RTC Time Seconds Register (RTC_TSR)
    543
  - RTC Time Alarm Register (RTC_TAR)
    544
  - RTC Control Register (RTC_CR)
    545
  - Freescale Semiconductor, Inc
    546
  - RTC Status Register (RTC_SR)
    547
  - RTC Lock Register (RTC_LR)
    548
  - RTC Interrupt Enable Register (RTC_IER)
    549
  - Functional Description
    550
  - Time Counter
    551
  - Time Alarm
    552
  - Update Mode
    553
    
    Freescale Semiconductor, Inc
    554
    
    Introduction
    555
    
    Modes of Operation
    556
    
    Block Diagrams
    557
    
    Freescale Semiconductor, Inc
    558
Chapter 34

559
- External Signal Description
  559
  - SPSCK — SPI Serial Clock
    560
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    561
  - Freescale Semiconductor, Inc
    562
  - SPI Control Register 2 (Spix_C2)
    563
  - SPI Baud Rate Register (Spix_Br)
    564
  - SPI Status Register (Spix_S)
    565
  - SPI Data Register (Spix_D)
    566
  - SPI Match Register (Spix_M)
    567
    
    Functional Description
    568
    
    Freescale Semiconductor, Inc
    569
  - Slave Mode
    570
  - SPI Transmission by DMA
    571
  - Freescale Semiconductor, Inc
    572
  - SPI Clock Formats
    573
    
    Freescale Semiconductor, Inc
    574
    
    Freescale Semiconductor, Inc
    575
  - SPI Baud Rate Generation
    576
  - Freescale Semiconductor, Inc
    577
  - Error Conditions
    578
  - Low Power Mode Options
    579
  - Reset
    580
    
    Interrupts
    581
    
    Initialization/Application Information
    582
  - Pseudo-Code Example
    583
    
    Freescale Semiconductor, Inc
    584
    
    Freescale Semiconductor, Inc
    585
    
    Freescale Semiconductor, Inc
    586
    
    Introduction
    587
    
    Modes of Operation
    588
    
    KL04 Sub-Family Reference Manual, Rev. 3.1, November
    589
  - I2C Address Register 1 (I2Cx_A1)
    590
  - I2C Frequency Divider Register (I2Cx_F)
    591
  - I2C Control Register 1 (I2Cx_C1)
    592
  - I2C Status Register (I2Cx_S)
    593
  - Freescale Semiconductor, Inc
    594
  - I2C Data I/O Register (I2Cx_D)
    595
  - I2C Control Register 2 (I2Cx_C2)
    596
  - I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
    597
  - I2C Range Address Register (I2Cx_Ra)
    598
  - I2C Smbus Control and Status Register (I2Cx_Smb)
    599
  - I2C Address Register 2 (I2Cx_A2)
    600
  - I2C SCL Low Timeout Register High (I2Cx_Slth)
    601
  - I2C Protocol
    602
    
    Freescale Semiconductor, Inc
    603
    
    Freescale Semiconductor, Inc
    604
    
    Freescale Semiconductor, Inc
    605
    
    Freescale Semiconductor, Inc
    606
  - Bit Address
    607
  - Address Matching
    608
  - System Management Bus Specification
    609
    
    Freescale Semiconductor, Inc
    610
    
    Freescale Semiconductor, Inc
    611
  - Resets
    612
  - Freescale Semiconductor, Inc
    613
  - Programmable Input Glitch Filter
    614
  - Address Matching Wakeup
    615
- Initialization/Application Information
  616
  - Freescale Semiconductor, Inc
    617
  - Freescale Semiconductor, Inc
    618
  - Introduction
    619
  - KL04 Sub-Family Reference Manual, Rev. 3.1, November
    620
  - Freescale Semiconductor, Inc
    621
- Register Definition
  622
  - UART Baud Rate Register High (Uartx_Bdh)
    623
  - UART Baud Rate Register Low (Uartx_Bdl)
    624
  - Freescale Semiconductor, Inc
    625
  - UART Control Register 2 (Uartx_C2)
    626
  - UART Status Register 1 (Uartx_S1)
    627
  - Freescale Semiconductor, Inc
    628
  - UART Status Register 2 (Uartx_S2)
    629
  - Freescale Semiconductor, Inc
    630
  - UART Control Register 3 (Uartx_C3)
    631
  - UART Data Register (Uartx_D)
    632
  - UART Match Address Registers 1 (Uartx_Ma1)
    633
  - UART Match Address Registers 2 (Uartx_Ma2)
    634
  - UART Control Register 5 (Uartx_C5)
    635
    
    Functional Description
    636
    
    Freescale Semiconductor, Inc
    637
  - Receiver Functional Description
    638
    
    Freescale Semiconductor, Inc
    639
    
    Freescale Semiconductor, Inc
    640
  - Additional UART Functions
    641
  - Freescale Semiconductor, Inc
    642
  - Interrupts and Status Flags
    643
    
    Freescale Semiconductor, Inc
    644
    
    Introduction
    645
  - Modes of Operation
    646
- Memory Map and Register Definition
  647

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