Analog Devices AD1887 Manual page 5

t
RST_LOW
RESET
BIT_CLK
Figure 1. Cold Reset
t
SYNC_HIGH
SYNC
BIT_CLK
Figure 2. Warm Reset
BIT_CLK
t
CLK_HIGH
t
SYNC
Figure 3. Clock Timing
t
SETUP
BIT_CLK
SYNC
SDATA_OUT
Figure 4. Data Setup and Hold
REV. 0
t
RST2CLK
t
RST2CLK
t
CLK_LOW
CLK_PERIOD
t
SYNC_LOW
t
SYNC_HIGH
t
SYNC_PERIOD
t
HOLD
BIT_CLK
t
RISECLK
SYNC
t
RISESYNC
SDATA_IN
t
RISEDIN
SDATA_OUT
t
RISEDOUT
Figure 5. Signal Rise and Fall Time
SLOT 1
SYNC
BIT_CLK
WRITE
TO 0x26
SDATA_OUT
SDATA_IN
NOTE: BIT_CLK NOT TO SCALE
Figure 6. AC Link Low Power Mode Timing
RESET
SDATA_OUT
SDATA_IN, BIT_CLK
Figure 7. ATE Test Mode
–5–
AD1887
t
FALLCLK
t
FALLSYNC
t
FALLDIN
t
FALLDOUT
SLOT 2
DATA DON'T
PR4 CARE
t
S2_PDOWN
t
SETUP2RST
HI-Z
t
OFF