Memory; Sdram; Serial Flash Memory With Spi Interface; Host Interface - Epson S5U13515P00C100 User Manual

Chapter 4 Technical Description

4.4 Memory

4.4.1 SDRAM

The S5U13515P00C100 evaluation board has 2 SDRAM ICs, each 128Mbit x16-bit, CL=2 in a TSOP54 package.
When the S2D13515 Display Controller is configured for 32-bit wide DRAM bus, both SDRAM ICs are used. When
the S2D13515 Display Controller is configured for 16-bit wide DRAM bus, only one of the SDRAM ICs is used
and the other SDRAM ICs is disabled by having its chip select input pulled high to inactive state, by putting jumper
JP16 in 2-3 position.

4.4.2 Serial Flash Memory with SPI interface

The S2D13515 Display Controller has a SPI Flash Memory interface which is connected to a 32Mbit Flash EPROM.

4.5 Host Interface

4.5.1 Direct Host Bus Interface Support

All S2D13515 host interface pins are available on connectors H3 and H4. This allows the S5U13515P00C100 evalu-
ation board to be connected to a variety of development platforms. For S2D13515 host interface pin mapping, refer
to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
The following figure shows the location of host bus connectors H3 and H4. H3 is a 0.1" x 0.1" 40-pin header (20x2)
and H4 is a 0.1" x 0.1" 34-pin header (17 x 2).
Figure 4-2: Host Bus Connector Location (H3 and H4)
For the pinout of connectors H3 and H4, see Section Chapter 6, "Schematic Diagrams" on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 17