SMC Networks SMC91C95 Product Manual page 83

8002h - Ethernet Configuration and Status Register (ECSR)
7 6
0 0
BIT 7 - Not defined
BIT 6 - Not defined
BIT 5 - IOIs8: This bit when set, indicates that
the Host can only do 8 bit cycles (on D7-D0).
The Ethernet function is forced in this case to
eight bit mode regardless of the nEN16 pin and
16BIT value. This bit also disables (floats) the -
IOIs16 signal.
BIT 4 - Not defined
BIT 3 - Not defined
BIT 2 - PwrDwn: When set (1), this bit puts the
SMC91C95 Ethernet function into powerdown
mode. The Ethernet function is also put into
powerdown mode when the Enable Function bit
(ECOR bit 0) is cleared. Refer to the
Powerdown Logic section for additional details
as to what logic is powered down.
BIT 1 - Intr: This bit is read/set to a one when
this function is requesting interrupt service. It is
cleared depending upon the setting of IntrACK.
5 4
IOIs8
0 0
When this bit and Enable IREQ Routing are set,
-IREQOut is asserted.
All setting and resetting of this bit is edge
triggered with exception of the internally
generated reset signal for the modem / Ethernet
related PC card registers. The Intr bit can be
reset the following ways and priority ranging
from 1=highest to 3=lowest:
1)
2)
3)
BIT 0 - IntrACK: This bit controls the clearing of
the Intr bit. When this bit is cleared, Intr reflects
the function's interrupt status. When this bit is
set, the Intr bit must be cleared by the host
writing a 0 into it.
additional service the Intr bit will remain
asserted when the host writes the 0.
83
3 2
Pwrdwn
0 0
A hardware reset/power up
The function ie. interrupt source can only
reset this field to zero (0) if the IntrACK
field is reset to zero (0)
The host system can only reset this field to
a zero (0) only if the IntrACK bit is set to a
one (1)
If the function requires
1 0
Intr IntrACK
0 0