Memory Partitioning; Interrupt Generation - SMC Networks SMC91C95 Product Manual

MEMORY PARTITIONING

Unlike other controllers, the SMC91C95 does
not require a fixed memory partitioning
between transmit and receive resources. The
MMU allocates and de-allocates memory
upon different events.
mechanism allows the CPU to prevent the
receive process from starving the transmit
memory allocation.
Memory is always requested by the side that
needs to write into it, that is: the CPU for
transmit or the CSMA/CD for receive.
CPU can control the number of bytes it
requests for transmit but it cannot determine
the number of bytes the receive process is
going to demand. Furthermore, the receive
process requests will be dependent on
network traffic, in particular on the arrival of
broadcast and multicast packets that might
not be for the node, and that are not subject to
upper layer software flow control.
In order to prevent unwanted traffic from using
too much memory, the CPU can program a
"memory reserved for transmit" parameter. If
the free memory falls below the "memory
reserved for transmit" value, MMU requests
from the CSMA/CD block will fail and the
packets will overrun
Whenever enough memory
packets can be received again.
reserved value is too large, the node might
lose data which is an abnormal condition. If
the value is kept at zero, memory allocation is
handled on first-come first-served basis for
the entire memory capacity.
Note that with the memory management built
into the SMC91C95, the CPU can dynamically
program this parameter. For instance, when
the driver does not
transmissions, it can allow more memory to
be allocated for receive (by reducing the value
of the reserved memory). Whenever the driver
An additional
The
and be ignored.
is released,
If the
need to enqueue
79
needs to burst transmissions it can reduce
the receive memory allocation. The driver
program the parameter as a function of the
following variables:
1) Free memory (read only register)
2) Memory size (read only register)
The reserved memory value can be changed
on the fly. If the MEMORY RESERVED FOR
TX value is increased above the FREE
MEMORY, receive packets in progress are
still received, but no new packets are
accepted until the FREE MEMORY increases
above the MEMORY RESERVED value.

INTERRUPT GENERATION

The interrupt strategy for the transmit and
receive processes is such that it does not
represent the bottleneck in the transmit and
receive queue management between the
software driver and the controller.
purpose there is no register reading necessary
before the next element in the queue (namely
transmit or receive packet) can be handled by
the controller. The transmit and receive
results are placed in memory.
The receive interrupt will be generated when
the receive queue (FIFO of packets) is not
empty and receive interrupts are enabled.
This allows the interrupt service routine to
process many receive packets without exiting,
or one at a time if the ISR just returns after
processing and removing one.
There are two types of transmit interrupt
strategies:
1) One interrupt per packet
2) One interrupt per sequence of packets
The strategy is determined by how the
transmit interrupt bits
RELEASE bit are used.
For that
and the AUTO