SMC Networks SMC91C95 Product Manual page 121

A0-15
AEN,
VALID ADDRESS
nSBHE
nIOCS16
nIORD
nIOWR
t9
Z
IOCHRDY
Z
D0-D15
t9 Control Active to IOCHRDY Low
t10 IOCHRDY Low Pulse Width*
t20 Cycle time**
*Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
**Note: The cycle time is defined only for accesses to the Data Register as follows:
For Data Register Read - From nIORD falling to next nIORD falling
For Data Register Write - From nIOWR rising to next nIOWR rising
FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES
t20
Z
t10
VALID DATA
Parameter
121
VALID ADDRESS
Z
min typ max
15
100 150
185
Z
VALID DATA
units
ns
ns
ns