Timing Diagrams; Data Valid - SMC Networks SMC91C95 Product Manual

A[5:0], nREG
nCE1
nOE
D[15:0]
t1
t2
t3
t4
t5
t6
NOTE: Applies only when nWAIT is asserted by the SMC91C95.

TIMING DIAGRAMS

t2
t3
t4
30 max
5 max
Parameter
Address Access Time
nREG Access Time
nCE1 Access Time
nOE Access Time
Output Disable Time from
nCE1 high
Output disable Time from nOE
high
FIGURE 18 - PCMCIA MEMORY READ TIMING
108
t1

DATA VALID

Min Typ Max
300
300
300
150
100
100
0 min
t5
t6
Units
ns
ns
ns
ns
ns
ns