SMC Networks SMC91C95 Product Manual page 45

I/O SPACE - BANK0
OFFSET
6 COUNTER REGISTER
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters
are cleared when reading the register and do not wrap around beyond 15.
HIGH
NUMBER OF EXC. DEFFERED TX
BYTE
0
LOW
MULTIPLE COLLISION COUNT
BYTE
0
Each four bit counter is incremented every time the
corresponding event, as defined in the EPH
STATUS REGISTER bit description, occurs. Note
that the counters can only increment once per
enqueued transmit packet, never faster, limiting the
rate of interrupts that can be generated by the
counters. For example if a packet is successfully
transmitted after one collision the SINGLE
COLLISION COUNT field is incremented by one. If
a packet experiences between 2 to 16 collisions,
the MULTIPLE COLLISION COUNT field is
incremented by one. If a packet experiences
NAME
0 0 0
0 0 0
45
TYPE
READ ONLY
NUMBER OF DEFFERED TX
0 0
SINGLE COLLISION COUNT
0 0
deferral the NUMBER OF DEFERRED TX field is
incremented by one,
experienced multiple deferrals during its collision
retries.
The COUNTER REGISTER facilitates maintaining
statistics in the AUTO RELEASE mode where no
transmit interrupts are generated on successful
transmissions.
Reading the register in the transmit service routine
will be enough to maintain statistics.
SYMBOL
ECR
0 0
0 0
even if the packet