SMC Networks SMC91C95 Product Manual page 62

I/O SPACE - BANK2
OFFSET
C INTERRUPT STATUS REGISTER
ERCV
INT
X 0
OFFSET
C INTERRUPT ACKNOWLEDGE
ERCV
INT
OFFSET
D INTERRUPT MASK REGISTER
ERCV
INT
X 0
This register can be read and written as a word or
as two individual bytes.
The Interrupt Mask Register bits enable the
appropriate bits when high and disable them when
low. An enabled bit being set will cause a
hardware interrupt.
EPH INT - Set when the Ethernet Protocol Handler
section indicates one out of various possible
special conditions. This bit merges exception type
of interrupt sources, whose service time is not
critical to the execution speed of the low level
drivers. The exact nature of the interrupt can be
obtained from the EPH Status Register (EPHSR),
NAME
RX_OVR
EPH INT
N INT
0 0
NAME
REGISTER
RX_OVR
N INT
NAME
RX_OVR
EPH INT
N INT
0 0
62
TYPE
READ ONLY
TX
ALLOC
EMPTY
INT
INT
0 1
TYPE
WRITE ONLY
TX
EMPTY
INT
TYPE
READ/WRITE
TX
ALLOC
EMPTY
INT
INT
0 0
and enabling of these sources can be done via the
Control Register. The possible sources are:
LINK_OK transition
CTR_ROL - Statistics counter roll over.
TXENA cleared - A fatal transmit error occurred
forcing TXENA to be cleared. TX_SUC will be low
and the specific reason will be reflected by the bits:
TXUNRN - Transmit underrun
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
SYMBOL
IST
TX INT RCV INT
0 0
SYMBOL
ACK
TX INT
SYMBOL
MSK
TX INT RCV INT
0 0