4-2-3 2ND LO LOOP
The 2nd LO circuit generates the 2nd LO frequencies, and
the signals are applied to the 2nd mixer circuit.
The generated signal at the VCO 3 (Q34) enters the PLL IC
(IC8, pin 13) via the buffer amplifier (Q35), is divided ath the
programmable divider seiction and is then applied to the
phase detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signals) from pin17
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (Q36, Q37), and then applied to the
VCO 3 to stabilize the oscillated frequency.
• PLL circuit
Q25, Q26
Phase
detector
X5
12.8 MHz
Programmable
divider
Phase
detector
Q36, Q37
Loop
filter
PLL IC (IC8)
Programmable
Prescaler
counter
Shift register/
data latch
Programmable
Prescaler
counter
Loop
filter
4-3 POWER SUPPLY CIRCUITS
4-3-1 VOLTAGE LINES
Line
The voltage from a DC power supply.
ACHV
The same voltage as the ACHV line which is
HV
controlled by the [POWER] switch.
Common 5 V line converted from the HV line by
+5
the +5 regulator circuit (IC16).
Common 8 V line converted from the HV line by
+8
the +8 regulator circuit (IC17).
Common 33 V line converted from the HV line by
the 33 V DC-DC convertor circuit (IC18). The
+33
output voltage is applied to the PLL circuit.
Common 5 V line converted from the ACHV line
L+5
by the L+5 regulator circuit (IC15).
Q24
Buffer
VCO1
IC26
Buffer
Q14, Q15
D39, D40
VCO2
Q18, Q19
D42, D43
Q27
Amp.
Pdat
Pck
PSTB
LPF
VCO3
Q35
Buffer
ATT
Q34
D72–D74
4 - 5
Description
L1AD to the CPU
to 1st mixer circuit
LPF
1st LO-freq.:
532.4–1066.65 MHz
Q22
IC6
Amp.
BPF
1/2
1st LO-freq.:
266.7–532.35 MHz
to 2nd mixer circuit
LPF
2nd LO-freq.:
255–257 MHz
ATT
Need help?
Do you have a question about the IC-PCR100 and is the answer not in the manual?
Questions and answers