Configuration; Block Diagrams; Figure 2.1 The Block Diagrams Of A Flash Memory; Table 2.1 Signal List - Toshiba TXZ Reference Manual

2. Configuration

Block Diagrams

The Block Diagrams of a Flash memory and a signal list are shown.
The clock for program/
erasing timing generation
f
IHOSC1
No Symbol
1
f
IHOSC1
2
INTFLCRDY0
3
INTFLCRDY1
4
INTFLDRDY
2018-06-05
Code Flash interface0
(FLASH I/F0)
Code Flash interface1
(FLASH I/F1)
Read buffer
Control circuit for Code Flash
（Include automatic sequence
control circuit）
Code Flash1
Security bit
Flash Protect Status
Register n
[FCPSRn]
n = 0,1,3,4
Flash Security Status
Flash Security Bit Flash Protect Mask
Mask Register Register n
[FCSBMR] [FCPMRn]
n = 0,1,3,4
Flash Area Selection
Register
[FCAREASEL]

Figure 2.1 The Block Diagrams of a flash memory

Table 2.1 Signal list

Signal name
The clock for program/erasing
timing generation
FLASH I/F0 Code FLASH
Ready interruption n
FLASH I/F1 Code FLASH
Ready interruption n
Data FLASH Ready
interruption
Flash Status
Register 0
[FCSR0]
Flash Buffer Disable
and Clear Register
[FCBUFDISCLR]
Code Flash0
User Information Area
Protect bit
Flash Bank Change
Memory SWAP bit
Flash Memory SWAP
Status Register
Flash Key Code
[FCSWPSR]
Register
KEYCODE
<
[FCSSR]
Flash Status Clear
Register
[FCSTSCLR]
I/O Related reference manual
Input Clock Control and Operation Mode
Output Exception
Output Exception
Output Exception
15 / 120
Data Flash interface (FLASH I/F2)
Control circuit for Data Flash
（Include automatic sequence
control circuit）
Data Flash
Protect bit
Register
[FCBNKCR]
Flash Protect Status
Register 6
[FCPSR6]
Register
[FCKCR]
>
Flash Protect Mask
Flash Control
Register 6
Register
[FCPMR6]
[FCCR]
Flash Status
Register 1
[FCSR1]
TXZ Family
Flash Memory
INTFLCRDY1
INTFLCRDY0
INTFLDRDY
Rev. 2.0