Lpc Connector - DFI CS630-H310 User Manual

LPC Connector

Battery
A61
A61
The Low Pin Count Interface was defined by Intel
sition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O com-
ponents within the system, which are typically provided by a Super I/O controller. Furthermore,
it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin Pin Assignment
1 L_CLK
3 L_RST#
L_FRAME#
5
L_AD3
7
L_AD2
9
INT_SERIRQ
11
5VSB
13
Chapter 2 Hardware Installation
Chapter 2
1
13
LPC
14 2
® Corporation to facilitate the industry's tran-
Pin Pin Assignment
L_AD1
2
L_AD0
4
3V3
6
GND
8
---
10
GND
12
5V
14
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