National Semiconductor ADC081500DEV Instruction Manual page 18

Out V
Low Amplitude – LVDS output voltage amplitude is set to 510mV pk-pk
High Amplitude – LVDS output voltage amplitude is set to 710mV pk-pk
OutEdge
Falling Edge – Data outputs are changed on the falling edge of DCLK+ (Single Data rate mode only)
Rising Edge – Data output are changed on the rising edge of DCLK+ (Single Data rate mode only)
DDR
Disable Dual Data Rate – DDR Mode is disabled (data output follows OutEdge Setting)
Enable Dual Data Rate – Data is output with rising and falling edge of DCLK (Default for 1.5GHz clock)
DES
Disable Dual Edge Sample – DES Mode is disabled.
Enable Dual Edge Sample – This Feature is not available on the single channel device
FSR
650mV Full Scale – Sets the full scale range to 650mV pk-pk
870mV Full Scale – Sets the full scale range to 870mV pk-pk
The Following Pull-down Tabs are available whether the Control mode is Hardware or Serial
Standby
Disable Standby – Enable all on-board power regulators
Enable Standby – Board is put into standby mode – All power is shutdown except USB power
PDQ
Disable Q Shutdown – Q Channel is not available
Enable Q Shutdown – Q Channel is not available
PD
Disable Shutdown – The ADC is powered up and Active
Enable Shutdown – The ADC is put into low power mode. Register Settings are retained
DC_Coup
AC Coupling – The I Channel is AC coupled to the ADCs input
DC Coupling – The I Channel is DC coupled to the ADCs input (not available on AC only model)
Ext_Clock
Internal Clock – The ADC is clocked using the on-board 1.5GHz clock
External Clock – The ADC is clocked from an External clock source connected to the "CLOCK" input.
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