Table of Contents
Related Manuals for National Semiconductor ADC081500DEV
Summary of Contents for National Semiconductor ADC081500DEV
- Page 1 March 24, 2006 Revision A Development Board Instruction Manual ADC081500DEV - Single 8-Bit, 1.5 GSPS, 1.2W A/D Converter with Xilinx Virtex 4 (XC4VLX15) FPGA © Copyright 2006 National Semiconductor Corporation www.national.com...
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Page 2: Table Of Contents
6.0 Evaluation Board Specifications ................... 5 7.0 Schematic Drawing ADC081500DEV – Onboard Clock (VCO + PLL) ......... 6 7.1 Schematic Drawing ADC081500DEV – Analog Inputs (I,Q) & Digital Trigger Input... 7 7.2 Schematic Drawing ADC081500DEV – ADC connected to Virtex4 FPGA ......8 7.3 Schematic Drawing ADC081500DEV –... -
Page 3: Introduction
The ADC connects to a Xilinx Virtex4 FPGA 1.0 Introduction which stores up to 4K of data from each The ADC081500DEV Board is designed to channel before transferring it through the USB allow quick evaluation and design development interface to the PC. -
Page 4: Quick Start
The ADC081500 Development Board schematic 3.0 Quick Start is shown in Section 7.0. Refer to Figure 1 for locations of the power connection, signal input and USB port. 4.1 Input circuitry IMPORTANT NOTE: The input signal(s) to be digitized should be applied to the front panel SMA connectors Install the Wavevision 4 Software before labeled “I CH.”... -
Page 5: Power Requirements
4.5 Power Requirements power supply requirement ADC081500 Evaluation Board is 12V at 800mA. Most of the regulators on board are switching regulators for increased power efficiency. The board typically draws around 500mA but it is always good practice to have extra power reserve in the power supply over the typical power requirements. -
Page 6: Schematic Drawing Adc081500Dev - Onboard Clock (Vco + Pll)
7.0 Schematic Drawing ADC081500DEV – Onboard Clock (VCO + PLL) www.national.com... -
Page 7: Schematic Drawing Adc081500Dev - Analog Inputs (I,Q) & Digital Trigger Input
7.1 Schematic Drawing ADC081500DEV – Analog Inputs (I,Q) & Digital Trigger Input www.national.com... -
Page 8: Schematic Drawing Adc081500Dev - Adc Connected To Virtex4 Fpga
7.2 Schematic Drawing ADC081500DEV – ADC connected to Virtex4 FPGA www.national.com... -
Page 9: Schematic Drawing Adc081500Dev - Usb Interface
7.3 Schematic Drawing ADC081500DEV – USB Interface www.national.com... -
Page 10: Schematic Drawing Adc081500Dev - Power Supplies 1
7.4 Schematic Drawing ADC081500DEV – Power Supplies 1 www.national.com... -
Page 11: Schematic Drawing Adc081500Dev - Power Supplies 2
7.5 Schematic Drawing ADC081500DEV – Power Supplies 2 www.national.com... -
Page 12: Schematic Drawing Adc081500Dev - Expansion Header Interface
7.6 Schematic Drawing ADC081500DEV – Expansion Header Interface www.national.com... -
Page 13: Bill Of Materials
8.0 Bill of Materials (Page 1 of 2) www.national.com... -
Page 14: Bill Of Material
8.1 Bill of Material (Page 2 of 2) www.national.com... -
Page 15: Using The Wavevision4 Software With The Adc081500Dev
“ON” position. The Green LED on the rear panel should be illuminated Connect the USB cable between the PC which has Wavevision 4 software installed and the ADC081500DEV board. The USB port can also be found on the rear panel (shown below). If this is the 1 time the board has been connected to the PC, Drivers may be required to be installed (automatic) by the Operating System. - Page 16 If the board is connected correctly the following popup box should appear to indicate that the board has been recognized and the firmware for the FPGA is being downloaded over the USB interface If the “Downloading firmware” box does not appear automatically, click on the “Settings” pulldown menu and then click Capture Settings as shown below.
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Page 17: Control Panel
The Following section describes the Function of the pull-down selection tabs in the left hand side of the ADC081500DEV product Control Panel Channel Selection I – Displays the data captured from the I Channel Only after acquiring Samples Q- Display is not available on this board due to the ADC being single channel I and Q –... - Page 18 Out V Low Amplitude – LVDS output voltage amplitude is set to 510mV pk-pk High Amplitude – LVDS output voltage amplitude is set to 710mV pk-pk OutEdge Falling Edge – Data outputs are changed on the falling edge of DCLK+ (Single Data rate mode only) Rising Edge –...
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Page 19: Serial Control Mode
Reset FPGA This button resets the FPGA, and also returns all the pulldown tabs to their default values Calibrate ADC This button issues an on-command calibration to the ADC by toggling the ADCs calibrate pin. 9.3 Serial Control Mode When the Hardware/Serial Control tab is selected as “Serial Register Program”, the control panel display will be changed to the following view. -
Page 20: Capturing Waveforms
9.4 Capturing Waveforms When the ADC has been configured as required, the selected input(s) can be sampled by clicking the “Acquire” pull-down menu and selecting “Samples”. Alternatively press F1 then the Escape key. 10.0 Appendix A - Hardware Information 10.1 LED functions The function of the LEDs on the front panel of the boards is as follows STB –... -
Page 21: Expansion Header
10.2 Expansion Header A 72 pin Future Bus Expansion Header is provided on the rear panel to allow easy connection to a third party microprocessor board to allow for the reading and analysis of the data captured by the FPGA. The signals connector to this expansion bus will be as follows DESCRIPTION DESCRIPTION... -
Page 22: System Block Diagram
10.3 System Block Diagram www.national.com... -
Page 23: Appendix B - Installing And Running The Wavevision 4 Software
11.0 Appendix B - Installing and running the Wavevision 4 software 11.1 Install the WaveVision Software. • Insert the WaveVision CD-ROM into your computer’s CD-ROM drive. • The WaveVision software requires a Java™ Runtime Environment or Java™ Development Kit, version 1.4 or higher, from Sun Microsystems, Inc. For detailed information on WaveVision’s use of Java technology, please see below. -
Page 24: Appendix C - Using Wavevision Plots
12.0 Appendix C - Using WaveVision Plots The WaveVision software provides several tools to help you interact with plots. A toolbar appears above each plot, similar to Figure 4. Figure 4: WaveVision Plot Tools Seen from left to right, the following tools are available: Plot Actions menu: This menu contains commands that pertain to this particular plot. -
Page 25: Fft Options
SNR, SINAD, THD, SFDR, and ENOB. These statistics are to be interpreted with the following definitions (which are repeated in every National Semiconductor ADC datasheet): Signal to Noise Ratio (SNR) is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. -
Page 26: Histogram Plots
Histogram Plots Histogram plots are created by counting the number of times each ADC output code appears in a dataset. Histograms may be computed by software, or by hardware. A software histogram is computed from a dataset which is normally 128k samples or smaller. A hardware histogram is collected directly by the hardware, and may include millions of counts per code. - Page 27 REFUND OF THE PURCHASE PRICE PAID, IF ANY. The ADC081500DEV Development Boards are intended for product evaluation purposes only and are not intended for resale to end consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for compliance with any other electromagnetic compatibility requirements.