Software Start Or External Input Clear Mode - LAPIS Semiconductor ML610Q174 User Manual

10.3.7.4 Software Start or External Input Clear Mode

With the setting of PnSTM1="1" and PnSTM0="1" on the PWMn control register 2 (PWnCON2), the PWM
counter operates being controlled by the PnRUN bit.
When there is no edge input on the external input (P00/PW45EV0 or P30/PW45EV1 or P01/PW6EV0 or
P31/PW6EV1 pin) selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2), the counter
operates in the same way as the software start. When the selected external input (P00/PW45EV0 or
P30/PW45EV1 or P01/PW6EV0 or P31/PW6EV1 pin) gets an edge input specified by PnTGE1 and PnTGE0,
the PWM counter is cleared. The PnCLIG bit of the PWMn control register 0 (PWnCON0) allows
enable/disable of the external clear input at the "H" level of the PWMn output flag (PnFLG).
Figure 10-10 shows the operation timing.
PnTGE1=0, PnTGE0=1
When falling-edge clear is selected
PnRUN
P00/PW45EV0
or
P30/PW45EV1
PWMn output
PWnCH/L
PWnPH/L
PWnPBUF
PWnDH/L
PWnDBUF
(a) Operation Timing Diagram with Software Start and External Input Clear
FEUL610Q174-01
The PnINI bit allows selection
of the "H/L" level for the PWM
initial value.
Count up
0000 Count up 0000
T
PWP
Software start
External input clear
Coincidence of the PWnCH/CL count value
and period buffer (PWnPBUF) value
2000
8000
8000
1000
4000
4000
Update buffer register
SFR write
from CPU
0000 Count up 0000 Count up
T T
PWP PWP
Coincidence of the PWnCH/CL count value
and period buffer (PWnPBUF) value
2000
1000
Update buffer register
SFR write
Update buffer register
from CPU
ML610Q174 User's Manual
Chapter 10
The PnSTPSEL bit allows selection of whether or not to output
the initial value while being paused
When the initial value is output, the PnINI bit allows selection
of the "H/L" level.
Hold value
Count up 0000
0000
Coincidence of the PWnCH/CL count value
and period buffer (PWnPBUF) value
8000
8000
4000
4000
Update buffer register
PWM
Count up
10-55