Appendix A Register Structure - Advantech ADAM-4500 User Manual

Function Description:
This function enables the watchdog timer function. After a user calls this function, the user must call the
wdt_clear() function to refresh the watchdog timer; otherwise the CPU resets, or a non-maskable interrupt
is generated.
wdt_clear
Syntax:
wdt_clear()
Function Description:
This function refreshes the watchdog timer, thereby avoiding the resetting of the CPU or the generation of
a non-maskable interrupt.
wdt_disable
Syntax:
wdt_disable()
Function Description:
This function disables the watchdog timer function.

Appendix A Register Structure

This appendix gives a short description of each of the ADAM-4500's registers. For more information
please refer to the data book for the STARTECH 16C550 UART chip.
All registers are one byte in length. Bit 0 is the least significant bit, and bit 7 is the most significant bit. The
address of each register is specified as an offset from the port base address (BASE), COM1 is 3F8h and
COM2 is 2F8h.
DLAB is the "Divisor Latch Access Bit", bit 7 of BASE+3.
BASE+0
BASE+0
BASE+0
BASE+1
The two bytes BASE+0 and BASE+1 together form a 16-bit number, the divisor, which determines the
baud rate. Set the divisor as follows:
Baud rate Divisor
50 2304
75 1536
110 1047
133.5 857
150 768
300 384
600 192
1200 96
1800 64
2000 58
Receiver buffer register when DLAB=0 and the operation is a read.
Transmitter holding register when DLAB=0 and the operation is a write.
Divisor latch bits 0 - 7 when DLAB=1
Divisor latch bits 8-15 when DLAB=1.
Baud rate
2400
3600
4800
7200
9600
19200
38400
56000
115200
Divisor
48
32
24
16
12
6
3
2
1