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Instruction
Mnemonic
Operand
group
Memory bit
SKTCLR
fmem.bit
manipulation
instructions
pmem.@L
@H+mem.bit
AND1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
OR1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
XOR1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
Note 1
Branch
BR
addr
instructions
addr1
!addr
$addr
$addr1
PCDE
PCXA
BCDE
BCXA
BRA
Note 1
!addr1
BRCB
!caddr
Notes 1.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the MK I mode.
2.
"0" must be set to the B register.
Number
Number
of machine
of bytes
cycles
2
2+S
Skip if (fmem.bit) = 1 and clear
2
2+S
Skip if (pmem
7–2
2
2+S
Skip if (H+mem
CY ← CY ∧ (fmem.bit)
2
2
CY ← CY ∧ (pmem
2
2
CY ← CY ∧ (H+mem
2
2
CY ← CY ∨ (fmem.bit)
2
2
CY ← CY ∨ (pmem
2
2
CY ← CY ∨ (H+mem
2
2
CY ← CY v (fmem.bit)
2
2
CY ← CY v (pmem
2
2
CY ← CY v (H+mem
2
2
← addr
–
–
PC
10–0
Select appropriate instruction among
BR !addr, BRCB !caddr, and BR $addr
according to the assembler being used.
← addr1
–
–
PC
10-0
Select appropriate instruction among
BR !addr, BRA !addr1, BRCB !caddr, and
BR $addr1 according to the assembler
being used.
← addr
3
3
PC
10–0
← addr
1
2
PC
10–0
← addr1
1
2
PC
10–0
← PC
2
3
PC
10–0
10-8
← PC
2
3
PC
10–0
10-8
← BCDE
2
3
PC
10–0
← BCXA
2
3
PC
10–0
← addr1
3
3
PC
10–0
← caddr
2
2
PC
10–0
µ PD754202, 754202(A)
Addressing
Operation
area
*4
+L
.bit(L
)) = 1 and clear
*5
3–2
1–0
.bit) = 1 and clear
*1
3–0
*4
+L
.bit(L
))
*5
7–2
3–2
1–0
.bit)
*1
3–0
*4
+L
.bit(L
))
*5
7–2
3–2
1–0
.bit)
*1
3–0
*4
+L
.bit(L
))
*5
7–2
3–2
1–0
.bit)
*1
3–0
*6
*11
*6
*7
+DE
+XA
Note 2
*6
Note 2
*6
*11
*8
10–0
Skip condition
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
41
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