NEC MuPD754202 Datasheet page 18

X1
System
clock
oscillator
X2
Oscillation stops
PCC
PCC0
PCC1
4
PCC2
HALT Note
PCC3
STOP Note
PCC2,
STOP F/F
PCC3
clear
Note Instruction execution
Remarks 1. f : System clock frequency
X
Φ = CPU clock
2.
3. PCC: Processor Clock Control Register
4. One clock cycle (t
18
Figure 6-1. Clock Generator Block Diagram
f
X
1/2 1/41/16
Q S
R
) of the CPU clock is equal to one machine cycle of the instruction.
CY
µ PD754202, 754202(A)
· Basic interval timer (BT)
· Timer counter
· INT0 noise eliminator
1/1 to 1/4096
Divider
HALT F/F
S
R Q
Wait release signal from BT
Reset signal
Standby release signal from
interrupt control circuit
Divider
Φ
1/4
· CPU
· INT0 noise
eliminator