NEC MuPD754202 Datasheet page 31

Hardware
Clock generator Processor clock control register (PCC)
Interrupt Interrupt request flag (IRQ×××)
function Interrupt enable flag (IE×××)
Interrupt master enable flag (IME)
Interrupt priority selection register (IPS)
INT0, 2 mode registers (IM0, IM2)
Digital port Output buffer
Output latch
I/O mode registers (PMGA, PMGC)
Pull-up resistor setting register (POGA, POGB)
Bit sequential buffer (BSB0-BSB3)
Hardware
Watchdog flag (WDF) Hold the previous status
Key return flag (KRF)
Table 9-1. Hardware Status After Reset (2/3)
Table 9-1. Hardware Status After Reset (3/3)
RESET signal RESET signal
generation by key generation in the
return reset standby mode
1
µ PD754202, 754202(A)
RESET signal generation
in the standby mode
0
Reset (0)
0
0
0
0, 0
Off
Cleared (0)
0
0
Held
RESET signal
generation by WDT
during operation
0 1
0 Hold the previous status
RESET signal generation
in operation
0
Reset (0)
0
0
0
0, 0
Off
Cleared (0)
0
0
Undefined
RESET signal
generation during
operation
0
0
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