Mitsubishi MELSEC-Q series Programming Manual page 98

S.PID
(4) PID operation
PID operation is performed with the following operation expression.
Item
When forward operation (PN=1)
Bn
When reverse operation (PN=0)
BW ( MV)
K : K × Gain (P), M : Derivative gain (MTD)
P D
T : Integral constant (I), T
I
In the following case, however, note that special processing will be performed.
QnPHCPU/QnPRHCPU (First 5 digits of
the serial No. : 07031 or earlier)
In either of the following cases 1, 2
1. Derivative constant (D) = 0 (T
2. Operation mode (MODE) is any of MAN, LCM and CMV
In any of the following cases 1, 2, 3
1. Integral constant (I) = 0 (T
2. When either of MHA or MLA is turned
to 1
CT
(MVP > MH) and ( DV
T
I
3. When either of MHA or MLA is turned
to 1
CT
(MVP < ML) and ( DV
T
I
(5) Deviation check
A deviation check is made under the following condition and the result of the check is output to DVLA of the alarm
detection (ALM) and the deviation large alarm (BB1) of the block memory.
Condition
DVL < |DV|
(DVL - DVLS) < |DV|  DVL
|DV|  (DVL-DVLS)
*1 When DVLI or ERRI in the alarm detection inhibition (INH) is set to 1, DVLA and BB1 show 0 since the alarm is prohibited.
(6) Loop stop processing
(a) Setting 1 in SPA of the alarm detection (ALM) selects a loop stop.
A loop stop performs the following processing and terminates the S.PID instruction.
1) BW is turned to 0.
2) DVLA of the alarm detection (ALM) is turned to 0.
3) The operation mode (MODE) is changed to MAN.
4) BB1 of BB are turned to 0.
(b) Setting 0 in SPA of the alarm detection (ALM) selects a loop run.
A loop run performs "(7) Control cycle judgment".
96
B +
n-1
B +
n-1
K {(DV
P
: Derivative constant (D)
D
Condition
QnPHCPU/QnPRHCPU (First 5 digits of
the serial No. : 07032 or later)
= 0)
D
= 0) In any of the following cases 1, 2, 3
I
1. Integral constant (I) = 0 (T
2. When either of MHA2 or MLA2 is turned to 1
0) (MVP > MH) and
n
3. When either of MHA2 or MLA 2 is turned to 1
(MVP < ML) and
0)
n
Operation expression
M ×T
D D
× {(PV - 2PV
n n-1
M ×CT+T
D D
M ×T
D D
× { - (PV - 2PV
n n-1
M ×CT+T
D D
CT
DV
DV B }
)
n n-1 n n
T
I
QnUDPVCPU
= 0)
I
CT
( DV 0)
n
T
I
CT
( DV 0)
n
T
I
Result
*1
DVLA = BB1 = 1
DVLA = BB1 = Last value status hold
DVLA = BB1 = 0
CT×B
n-1
+ PV ) - }
n-2
T
D
CT×B
n-1
+ PV ) - }
n-2
T
D
Processing
Bn = 0
(However, the loop tag
past value memory is
set.)
CT
DV 0
n
T
I
*1