Mitsubishi MELSEC-Q series Programming Manual page 123

(5) Deviation check
A deviation check is made under the following condition and the result of the check is output to DVLA of the alarm
detection (ALM) and the deviation large alarm (BB1) of the block memory.
Condition
DVL < |DV|
(DVL - DVLS) < |DV|  DVL
|DV|  (DVL - DVLS)
*1 When DVLI or ERRI of the alarm detection inhibition (INH) is 1, DVLA and BB1 turn to 0 since the alarm is inhibited.
(6) Loop stop processing
(a) Setting 1 in SPA of the alarm detection (ALM) selects a loop stop.
A loop stop performs the following processing and terminates the S.SPI instruction.
1) BW is turned to 0.
2) DVLA of the alarm detection (ALM) is turned to 0.
3) The operation mode (MODE) is changed to MAN.
4) BB1 of BB are turned to 0.
(b) Setting 0 in SPA of the alarm detection (ALM) selects a loop run.
A loop run performs "(7) Operating time/hold time check judgment ".
(7) Operating time/hold time check judgment
Whether it is the operating time (ST) or hold time (HT = STHT - ST) is judged and the following processing is performed.
(a) Operating time (ST)
SV setting processing, tracking processing, gain (Kp) operation processing, PI operation (operating time) and
deviation check are performed.
(b) Hold time (HT = STHT - ST)
Tracking processing, SPI operation (hold time) and deviation check are performed.
Under the following condition, however, the hold time is set to 0 and continuous PI control is carried out.
STHT ST
T T
When the integer part of
Operation Error
In the following cases, the error flag (SM0) turns ON and the error code is stored in SD0.
Error code
When an operation error occurs
When the values of
non-normalized number
4100
When the execution cycle ( T) < 0
When the operating time (ST) < 0
When the sample counter < 0
When the values of
4140
non-normalized number
4141 When an operation error occurs
DVLA = BB1 = 1
DVLA = BB1 = Last value status hold
DVLA = BB1 = 0
STHT
is 0, no processing is performed. ( MV also remains unchanged.)
T
Error definition
, , are either a non-numeric or
S1 S2 D2
, , are either a non-numeric or
S1 S2 D2
Result
*1
*1
QnPHCPU QnPRHCPU
–– ––
–– ––
S.SPI
9
2
3
4
4
6
7
8
QnUDPVCPU
––
––
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