Hitachi KP-FM500WCL Operation Manual page 39

（４）Deca（10TAP） Configuration
（ａ）8bit
D.OUT1
TXCLKOUT
TXOUT 3
TXOUT 2
TXOUT 1
TXOUT 0
D.OUT2
TYCLKOUT
TYOUT 3
TYOUT 2
TYOUT 1
TYOUT 0
TZCLKOUT
TZOUT 3
TZOUT 2
TZOUT 1
TZOUT 0
T 11.765 ns (85MHz) or 16.667ns (60MHz)
CLK
Previous Cycle
DA5-1 DD1-1 DC7
DC4-1 DC3-1 DD0
DB1-1 DB0-1 DC2
DA1-1 DA0-1 DA7
T 11.765 ns (85MHz) or 16.667ns (60MHz)
CLK
Previous Cycle
LVAL-1
DD7-1 DG1
DF6-1 DF5-1 DG4
DE3-1 DE2-1 DF4
DD3-1 DD2-1 DE1
T 11.765 ns (85MHz) or 16.667ns (60MHz)
CLK
Previous Cycle
LVAL-1
DH2-1 DJ4
DJ1-1 DJ0-1 DJ7
DH6-1 DH5-1 DI7
DG6-1 DG5-1 DH4
Next Cycle
DC1 DC0 DB3
FVAL LVAL DC6
DB7 DB6 DB5
DA6 DA4 DA3
Next Cycle
DF3 DF2 DE5
DG3 DG2 DG0
DF1 DF0 DE7
DE0 DD6 DD5
Next Cycle
DI6 DI5 DI0
DJ6 DJ5 DJ3
DI4 DI3 DI2
DH3 DH1 DH0
DB2 DA5 DD1
DC5 DC4 DC3
DB4 DB1 DB0
DA2 DA1 DA0
N.U.: Not Used
DE4 DD7 LVAL
DF7 DF6 DF5
DE6 DE3 DE2
DD4 DD3 DD2
N.U.: Not Used
DH7 DH2 LVAL
DJ2 DJ1 DJ0
DI1 DH6 DH5
DG7 DG6 DG5
N.U.: Not Used
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