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The unit select lines, USA and USB, are decoded by the 74S139 decoder (A56 on sheet 3) to generate the drive
select signals. The decoder outputs are inverted and driven by 7438 gates (A17) at the DRV SEL lines to the drives
(J1 - 46, J1 - 48, J1 - 50, J1 - 52). The HEAD LOAD/ signal (I.C. A46 - 4 on sheet 4) gates the DRV SEL
signals. The decoder outputs are also used as inputs to the drivers for the drive select LED indicators (LED/ lines
at J1 - 54, 66, 64, 68). These lines are also gated by the HEAD LOAD/ signal.
The HEAD LOAD latch is set by the LDHD/ control pulse (A47 - 3) which is generated by the microprogram being
executed on the Channel Board (see Table 3-3). The LOAD latch is cleared by the UNLHD/ pulse (A47 - 11) which
is also generated by the microprogram.
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After loading the read/write head on the selected drive, the head must be positioned over the proper track. Any of the
seven diskette operations will cause the diskette controller to seek the track specified in the I/O Parameter Block (IOPB),
prior to actually performing the operation (refer to Chapter 2).
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The direction of head movement is defined by the level on the DIR/ lines (pins J1 — 6, J1 — 8 on sheet 4). The
DIREC control level (I.C. A58 - 11), maintained by the microprogram (see Table 3-3), is applied to the 7438 NAND
gates in the disk drive control block. The outputs from these 7438 gates (A11 — 3, A11 — 6) drive the DIR/ lines.
Each pulse on the STEP/ lines (pins J1 — 2, J1 — 4) will cause the read/write head on the selected unit to move one
track either in or out depending on the level of the DIR/ lines. When DIR/ is high, the head will move one track away
from the center of the diskette. When DIR/ is low, the head will move one track closer to the center.
The STEP/ pulse is defined by the output of a 9602 one-shot (at A61 - 10). This one-shot is triggered by the CSTEP
control pulse, generated by the microprogram (see Table 3-3), unless the read/write head at the selected unit is already
over track 0 (the outermost track) while the DIR/ line indicates outward movement. If the head on the selected unit
is loaded, the output from the one-shot will produce a 10 usec. pulse on the STEP/ line, as shown in Figure 4-2.
After the head has been positioned over the proper track (by pulsing STEP/ the required number of times), the
diskette controller must wait at least 20 msec, before it begins examing the read data in an attempt to detect the ID
address mark which precedes an address field. Reading the address field will verify that the seek operation placed
the head over the proper track. Read initiate timing is illustrated in Figure 4-3.
The disk drive control block also includes a 9602 one-shot (at A61 — 7) which produces a 10 msec. TIMEOUT pulse,
which is made available to the Channel Board (pin P2 — 38) for use by the microprogram. The microprogram triggers
this one-shot by generating the SSCLK control pulse (see Table 3-3). Ten milliseconds after SSCLK triggers the one-
shot, a low-to-high transition from the Q output of the one-shot will appear on the TIMEOUT line.
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The disk drive control block drives the INOP RESET/ lines (pins J1 - 60 and J1 - 62) and the TRACK>43/ lines
(pins J1 — 56 and J1 — 58) to the diskette drives under control of the microprogram. The TRACK>43 latch
(I.C. A46 — 7 on sheet 1) is set by the GTR43/ pulse (A59 — 3) which is generated by the microprogram (see Table 3-3).
The latch is reset by the NGTR43/ pulse (A59 - 6). The WFLRS level (I.C. A58 - 2) is maintained by the micro-
program and drives the 7438 gates which in turn drive in INOP RESET/ lines to the drives. INOP RESET/ resets the
FILE INOP/ lines driven by the selected drive. TRACK>43/ forces the selected drive to reduce the write current on
inner tracks of the diskette.
The disk drive control block accepts the TRACKO/, INDEX/, FILE INOP/, and WPROT/ lines from the diskette
drives and passes them to the Channel Board for use by the microprogram. TRACKO/ (pin J1 — 38 or J1 — 44
depending on which drive is selected) is merely inverted twice and output as TRACKOO/ at pin P2 — 11. INDEX/
(pin J1 - 42 or J1 - 40) is inverted and clocks a 7474 latch to the set state. The Q output of this latch drives
the INDEX line (pin P2- 42) to the Channel Board. The microprogram can reset the INDEX latch by generating
4-4
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