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TABLE 3-3
CONTROL PULSES AND LEVELS GENERATED BY MICROPROGRAM
OUT CODE
(DEC OUT n)
MASK BIT
MO
M1
M2
M3
t-^.
M4
M5
M6
000
(0)
CSTEP
SSCLK
LDHD
001
(1)
RDYRS
_.
RINH
SINH
SACK
RDOR
010
(2)
NSUBO
NSUB1
- — --
-
'
011
(3)
LDNXM
WTGTN
SR OUT
LDADM
100
(4)
_
-_. -
CRC MD
DIREC
101
(5)
AMWRT
WFLRS
— ~.-
?
_
LOWEN
MEMWT
•
i
i
110
(6)
SMREQ
STBDU
STBDL
LDADD
GTR43
SINTR
CINBS
111
(7)
CSYNC
RSAMD
UNLHD
RSTST
NGT43
RNDX
LDOPC
CONTROL FUNCTION DEFINITIONS
CSTEP
SSCLK
LDHD
RINH
SINH
SACK
This pulse triggers the one-shot which drives the STEP/ line to the diskette drives.
STEP/ causes the selected drive to move its head one track.
i
This pulse triggers the TIMEOUT one-shot. TIMEOUT provides a 10 msec, pulse
for use by the microprogram.
. . . . _ , .
This pulse sets the LOAD latch on the Interface Board which causes the read/write
head on the selected unit to be loaded.
t, '
*
This pulse resets the inhibit memory write latch (A48—1).
L,,.
?
This pulse sets the inhibit memory write latch (A48—4).
" ~
This pulse sets the transfer acknowledge (XACK/) latch on the Interface Board.
RDOR
—
This pulse resets the data overrun latch on the Interface Board.
-.
NSUBO and NSUB1
-
These levels select 'primary instruction bus' inputs to 3001 MCU.
LDNXM
-
WTGTN
rc
r
-.t
This level is used to load the clock shift register with the bit patterns required to
write the different address marks onto a diskette.
When the data and clock shift registers are empty, this level allows both shift registers to
be parallel loaded with information that will be serially shifted out to the Interface Board
and then to the diskette. Used to generate PE/ and WRT GT/ signals.
3-10
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