Intel INTELLEC Hardware Reference Manual page 42

TABLE 3-3 (CONTINUED)
CONTROL FUNCTION DEFINITIONS (CONTINUED)
SROUT - This level enables data bits from data register (when high) or from 9401 CRC device (when
low) to be sent to the selected diskette.
LDADM -
This level is used to load clock shift register with the bit patterns required to write the
different address marks onto a diskette.
CRCMD This level indicates the operating mode for the 9401 CRC device on the Interface
Board.
DIREC — This level indicates the direction of head movement for the selected diskette drive.
AMWRT — This level enables writing of an extra clock pulse and is activated during writing of an
address mark. - ~ ,„
LOWEN
STBDL
LDADD
This level drives the GATE LOWER line that enables data onto the memory data inputs
(MO/ - M7/) to the CPE array.
MEMWT — This level indicates when the Diskette System wishes to write data to memory.
SMREQ — This pulse initiates the bus request sequence intended to gain master control of the
INTELLEC MDS system bus. . |
I
STBDU — This pulse loads CPE data outputs (DO — D7) into the latch which drives the system data
lines, DATA8/ - DATAF/.
This pulse loads CPE data outputs (DO — D7) into the latch which drives the system data
bus lines, DATAO/ - DATA?/. J
This pulse loads CPE data outputs (DO — D7) into the latch which drives the system
address bus lines, ADRO/ - ARD7/.
:
.
{
SINTR This pulse is used to generate a signal which clocks the interrupt latch on the Channel
Board.
CINBS — This pulse is used to latch data from the system data bus into the latches which drive
M0 - M7/ of the CPE array.
CSYNC — This pulse initializes the synchronization logic prior to detecting an address mark.
RSAMD — This pulse resets the synchronization logic prior to initializing the logic with the CSYNC
pulse.
UNLHD - This pulse clears the LOAD latch on the Interface Board, and ultimately causes the read/
write head on the selected drive to be unloaded.
RSTST This pulse is used to generate CLR START STOP signal which resets the STOP latch and
the 74145 latch at A8-1 on the Channel Board.
RNDX - This pulse resets the INDEX latch on the Interface Board.
LDOPC — This pulse latches diskette operation code (DO—D5) and makes latched code available to
'primary instruction bus' multiplexer.
3-11