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Recall from Chapter 2, that the CPU specifies channel operations for the Diskette System by executing one of the
seven channel commands. A channel command may be the result of either an input or output instruction to a
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dedicated I/O port address on the Channel Board:
1)
Write MA Lower (output to 'BASE+1')
2)
Write MA Upper and start I/O (output to 'BASE+2')
3)
Stop Diskette Operation (output to'BASE+3')
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^
4)
Reset Channel (output to 'BASE+7')
5)
Read Subsystem Status (input to 'BASE+0')
6)
Read Result Type (input to'BASE+1')
. . . . . .
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7)
Read Result Byte (input to 'BASE+3')
The three least significant bits (ADRO/ - ADR2/) of the 8-bit I/O address (received at pins P1-51 through P1-58)
differentiate between the various input or output channel commands. The five most significant address bits (ADR3/
A D R 7 / ) select the Channel Board if they match the BASE address that is assigned by setting five positions of switch
S1. These five switch positions each feed one input on five EXCLUSIVE-OR gates. If ADR3/ - A D R 7 / match the
switch-selected BASE address, the 7410 NAND gate (A31 -8) is activated and, in turn, enables one of the two 3205
decoders.
\~^s
If an input channel command is being received, the RD CMD line (pin P2-60) will be true, and the 3205 decoder at
A20 will be enabled. Address bits A D R O — A D R 2 (once inverted) are applied to the three data inputs on the 3205
section (AO — A2), and activate one of three inverted outputs (Og, 0^ or 03), depending on the channel command.
If it is 'read subsystem status' command, output 0 goes true and READ INT/ is asserted at pin P2-57. (On the Inter-
face Board, READ INT/ is used to gate the device D and device 1 ready indicators onto system data bus lines 0 and
1, DAT0/ and DAT1/.) The low level on READ INT/ also enables two 8093 circuits, one of which transmits the
output of the interrupt latch (INT/) to the data bit 2 line (DAT2/) of the system data bus. The other 8093 circuit
transmits a low-level to the data bit 3 line (DAT3/), indicating that the diskette controller is present. INT/ is also
passed to the Interface Board via pin P2-40.
^—
If a 'read result type' command is being received, output 1 from the decoder goes true, and the RD Rl/ signal is
generated (pin P2-37). The low level on RD Rl/ pre-sets the interrupt latch (A37-1 0), thus removing the active-low
system interrupt request (INT/).
The interrupt latch can subsequently be clocked reset (i.e., reset to the active-low state) by a pulse on the CLK line,
when the central processing element block (Section 3.2.4) determines that an 'I/O complete' or 'ready status change'
"^
interrupt should be issued (also refer to Chapter 2).
If a 'read result byte' command is being received, output 3 from the decoder will go true, and the 741 75 quad
latches are clocked, latching up address bits ADRO — ADR2. The three most significant quad latch outputs are
made available to the micro control unit block (Section 3.2.2), which responds to this command via a routine
stored in microprogram memory. Either read result command will generate the RD RES/ signal which is used by
the data flow control block (Section 3.2.6) to gate the appropriate status word onto the system data bus.
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If an output channel command is being received, the WRT CMD line (pin P2-53) will be true, and the other 3205
decoder will be enabled. Address bits ADRO - ADR2 are applied to inputs AO - A2, causing one of the eight
inverted decoder outputs to go true. If outputs 0, 1 or 2 go true, the WSUB1/ line (pin P2-48) is activated. If outputs
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4, 5 or 6 from the decoder go true, the WSUB2/ line (pin P2-47) is activated. Either WSUB1/ or WSUB2/ will cause
the 74175 quad latches to be clocked and latch up address bits A D R O — ADR2, just as a 'read result byte' command
did. The three most significant outputs of the quad latches are made available to the micro control unit block which
responds to the 'write MA lower', the 'write MA upper and start I/O' and the 'read result byte' channel commands,
using routines stored in microprogram memory. The response mechanisms for the other channel commands are
implemented in hardware, not microcode.
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3-4
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