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TABLE 3-3 (CONTINUED)
- - CONTROL FUNCTION DEFINITIONS (CONTINUED) - -
RDYRS
—
This pulse resets the Drive Ready flip-flops on the Interface Board.
( " - • ' • " ..',•
' ,
; •
• •«
•'
- ' • • , > . -
WFLRS
—
This level generates the write fault reset pulse to the selected drive.
GTR43
—
This pulse sets the low current mode for writes on tracks greater than 43-|rj-
NGT43
—
This pulse resets the low current mode for writes on tracks equal to or less than 43-|0-
TABLE 3-4 I-BUS SELECTION BY MASK FIELD BITS
MASK BITS
M7 =
M6 =
M5 =
M4 =
M3 =
INPUT FIELDS*
DATA SHIFT REGISTER
(A36 and A29)
OUTPUTS
1
0
o
1
0
CLOCK SHIFT REGISTER
(A34 and A27)
<"•• OUTPUTS
1
0
- -
o
••••—'
1
1
ERROR LINES
(DOR, WRT PROT,
WRT ERR, SEL
DR NRDY)
1
1
0
0
0
STATUS LINES
(DRO, DR1, STOP,
TRACKOO)
1
1
1
0
0
* An input field will be multiplexed into the I inputs of 3002 CPE array if the mask bits reflect the values listed for
that field and if the K-Bus select line, SO (bit 9 of the current microinstruction) is high (logical 1). Refer to Sec-
tion 3.2.4 for a more complete description of the 3002 CPE array inputs.
3)
Providing generalized inputs to the K-bus inputs of the 3002 CPE array. The mask bits
are multiplexed through two 8234 multiplexer devices and into K-bus inputs of the CPE
;
:
array. The selection bits are provided by SO and S1 (bits 9—10 of the current micro-
instruction). Table 3—5 correlates the levels on the SO and S1 lines with the K-bus inputs.
3.2.4
Central Processing Element (CPE) Block
;
The central processing element (CPE) block executes the function indicated by each microinstruction output from
the microprogram memory. The CPE block includes an array of four Intel 3002 Central Processing Elements, as
well as four 8234 and one 8233 eight-to-four multiplexers that provide various inputs to the CPE array, as shown
on sheet 4 of the board schematic (Section 3.3).
3-12
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