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The parallel inputs to the first data shift register (A36) are supplied by the four least significant data outputs from
the CPE array, as follows:
DO
^ PO
D1
V
P1
D2
>•
P2
> r
"""" "
:
'
The parallel inputs to the second data shift register (A29) are supplied by the four most significant CPE array data
outputs:
,
L/t
nF>
UD
DR
UD
r>7
—
^~
i \j
>. pi
"
Y \
•to.
P9
^
I <^
^.
PQ
The data bits can then be_ shifted out, in serial, to the Interface Board via the SR DATA OUT line (pin P2-25)
which is driven by the Q3 output on the second data shift register.
During read operations, the Interface Board sends the clock bits (that were interleaved with the data bits on the
diskette) to the Channel Board via the_SR CLK IN/ line (pin P2-6) along with the clock strobe, CLK SR STB (pin
P2-8). SR CLK IN/ feeds the J and K inputs on the first clock shift register at A34. The Q3 output of this first
clock shift register then feeds the J and K inputs on the shift register at A27. When the clock shift registers are full,
the eight clock bits can be transferred in parallel to the CPE array. The four outputs from the first clock shift
register (A34) are applied to the 'B' inputs on the 8233 multiplexer that feeds the four least significant bits of the
l-bus to the CPE array. The four outputs from the second clock shift register (A27) are applied to the 8234 multi-
plexer that feeds the four most significant bits of the l-bus. Both clock shift registers are clocked by CLK SR STB.
During write operations, both clock shift registers can be parallel loaded when the PE/ signal (described above) is low.
The PO, P1 and P2 inputs to the first clock shift register and the P2 and P3 inputs to the second clock shift regis-
ter are tied to ground. The P3 input to the first shift register and the P1 input to the second are both fed by the
output of a 7408 AND gate (A7-6) shown on sheet 3 of the schematic. The inputs to this gate are the LDNXM
and LDADM control levels which have been set in the 3404 latches at A16 by the microprogram (refer to Table 3—3).
The PO input to the second clock shift register is fed by the LDADM control output. LDNXM and LDADM allow
the microprogram to produce the varied patterns of clock bits that are required to write the different types of
address marks onto a diskette (refer to Section 1.2).
3.2.6
Data Flow Control Block
> r
' ''- -
The data flow control block routes data to/from the various other functional blocks within the Channel Board. This
block consis'ts of five 8212 bi-directional latching bus drivers, a 3404 six-bit latch and various gating circuits, as
shown on sheet 2 of the board schematic (Section 3.3).
. -t
The six least significant data outputs (DO — D5) from the CPE array are applied to the inputs of the 3404 six-bit
latch. When the_ microprogram generates the LDOPC control pulse (see Table 3-3),
DO - D5 are latched and in-
verted. DO - D2 are made available to the 'primary instruction bus' multiplexer (A5) in the MCU block. D3 is
used for 16-bit data flow control as described below. D4 and D5 are sent to the Interface Board as the unit select
signals, USA (pin P2-9) and USB (pin P2-12), respectively.
All eight CPE data outputs, DO - D7, are also applied to three of the 8212 latching bus drivers. DO - D7 are loaded
into the 8212 device at A41 when the microprogram generates the LDADD control pulse (see Table 3—3). The 8212
3-16
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