Intel iSBC 86/05 Manuals

Manuals and User Guides for Intel iSBC 86/05. We have 1 Intel iSBC 86/05 manual available for free PDF download: Hardware Reference Manual

Intel iSBC 86/05 Hardware Reference Manual (192 pages)

SINGLE BOARD COMPUTER

Brand: Intel | Category: Desktop | Size: 3 MB

Table of Contents
5
Introduction
11
Description
12
Additional Equipment Required
14
Compliance Level: 796 Bus Specification (IEEE Standard)
14
COMPLIANCE LEVEL: INTEL Isbx BUS SPECIFICATION
14
Specifications
14
Board Specifications
15
Installation Considerations
19
Introduction
19
Isbc® 86/05 Single Board Computer
19
Minimal Operating Requirements
19
Preparation for Use
19
Unpacking and Inspection
19
Cooling Requirements
20
Memory Allocation Considerations
20
Power Requirements
20
System Considerations
20
Clock Generator
21
Fail-Safe Timer Selection
21
Processor Clock
21
Timing Considerations
21
Common Bus Request
22
Interface Arbitration
22
Interval Timers
22
Priority Resolution Considerations
23
Serial Priority Resolution
24
Serial Priority Resolution Schemes
25
Parallel Priority Resolution
26
Parallel Priority Resolution Scheme
27
Bus Vectored Interrupts
28
Interface Considerations
28
Multibus~ Interface
28
Non-Bus Vectored Interrupts
28
Is BX'" Interface Considerations
29
Jumper Configurations
29
Parallel I/O Considerations
29
Serial I/O Considerations
29
Isbc~ 86/05 Jumpers
32
Memory Jumper Information
38
Page Select Jumpers
38
PROM Configurations
38
ROM/PROM Configurations
39
RAJ1 Configuration Considerations
40
Interval Timer Input Jumper Configurations
41
Connector J2 Pin Assignments
42
Serial Port Jumper Configurations
42
Serial Port Jumper Connections
42
Connector J2 Pin Assignments
43
Parallel Port Default Jumper Connections
44
Parallel Port Jumper Configurations
45
Parallel Port C Jumper Configurations
46
Parallel Port Jumpers & Restrictions
47
Interrupt Matrix Jumper Configurations
52
51Rxintr
53
Interrupt Matrix Jumper Configurations
53
Pb Intr
53
Multibus® Interrupt Output Jumper Configuration
54
External Interrupt 0 (EXT INTRO)
55
Math Interrupt (MINT)
55
Non-Maskable Interrupt Input Mask
55
Power Fail Interrupt (PFIN/)
55
Power Line Clock (PLC)
55
Multibus~ Interrupt Output Option (BUS INTR OUT)
56
Multibus~ Vectored Interrupts
56
BCLK and CCLK Jumper Configurations
57
Bus Clock & Constant Clock Selection
57
On-Board Timing Jumper Selection
57
Wait State Generator Selection
57
Bus Arbiter Jumper Configuration
58
Isbx'· Multimodule Board Mode Jumper Selection
58
Power Fail Battery Backup Provisions
60
Installation
61
ROM/PROM Installation
61
Line Drivers & I/O Terminators
62
ROH/PROM Device Insertion
62
Isbc~ 341 PROM/ROM Expansion Module Installation
63
Isbc& 302 RAM }1Odule Installation
64
Isbc® 341 Module Insertion
64
Isbc® 302 Module Insertion
65
Isbx'· Multimodule'· Board Installation
65
Connector Information
66
Final Installation
66
Parallel I/O Cabling
66
Serial I/O Cabling
67
User Furnished Connector Details
68
Bulk Cable Types
69
RS232 Signals Pin Correspondence
71
Introduction
73
Memory Addressing
73
On-Board ROM Addresses
73
Programming Information
73
I/O Addressing
74
On-Board RAM Addresses
74
System Initialization
74
I/O Port Addresses
75
8253 Interval Timer Programming
76
Addressing
77
PIT Register Address
77
Typical PIT Control Word Subroutine
78
PIT Mode Control Word Format
79
Typical PIT Counter Value Load Subroutine
80
PIT Counter Register Latch Control Word Format
81
Typical PIT Counter Read Subroutine
81
Mode Control Word Count
82
PIT Programming Sequence Examples
82
Operation
84
PIT Counter Operation Vs Gate Input
84
Clock Frequency/Divide Ratio Selection
85
Counter Read
85
Count Values and Rate Multipliers
86
PIT Baud Rate Factors
87
PIT Rate Generator Frequencies and Timer Intervals
88
Rate Generator/Interval Timer
88
8251A PCI Programming
89
Interrupt Timer
89
PIT Timer Intervals & Timer Counts
89
Mode Instruction Fa Rma T
90
Sync Characters
90
PCI Asynchronous Mode Instruction Word Format
91
PCI Asynchronous Mode Transmission Format
92
Command Instruction Format
93
PCI Command Instruction Word Format
93
Addressing
94
Reset
94
Initialization
95
Typical PCI Initialization Subroutine
96
Operation
98
Typical PCI Command Instruction Subroutine after Initialization
99
Typical PCI Data Character Read Subroutine
99
Typical PCI Data Character Write Subroutine
100
Typical PCI Status Read Subroutine
100
PCI Status Read Format
101
Control Word Format
102
Parallel Port Configuration
102
Parallel Port I/O Addresses
103
PPI Control Word Format
103
Addressing
104
Initialization
104
Operation
104
PPI Port C Bit Set/ Reset Control Word Format
105
Single Bit Set/Reset Feature
105
Typical PPI Initialization Subroutine
106
Typical PPI Port Read Subroutine
106
Typical PPI Port Write Subroutine
106
8259A PIC Programming
107
Parallel I/O Interface Configurations
107
Automatic Rotating Mode
108
Fully Nested Mode
108
Interrupt Priority Hodes
108
Special Fully Nested Mode
108
Special Hask Hode
108
Specific Rotating Mode
108
Initialization Command Words
110
Status Read
110
PIC Initialization Command Word Formats
111
Interrupt Vector Byte
113
3.8.5 Addressing
114
Operation Command Words
114
Initialization
115
PIC Operation Control Word Formats
116
Typical PIC Initialization Subroutine (NBV Mode)
117
Typical Slave PIC Initialization Subroutine (BV Mode)
118
PIC Operation Procedure
119
Operation
120
Typical PIC Interrupt Request Register Read Subroutine
122
Typical PIC In-Service Register Read Subroutine
123
Typical PIC Mask Register Read Subroutine
123
Typical PIC Set Mask Register Subroutine
123
8086 Interrupt Handling
124
Typical PIC End-Of-Interrupt Command Subroutine
124
Maskable Interrupt (INTR)
125
Master PIC Byte Identifier
125
Non-Maskable Interrupt (NMI)
125
Slave PIC Byte Identifier
126
Introduction
127
Service and Repair Assistance
127
Replacement Parts
128
Service Diagrams
128
Internal Signals
129
Jumper Locations
129
Isbc~ 86/05 Replacement Parts List
130
List of Internal Signal Mnemonics
132
Manufacturer's Names
132
Interface Signal Information
167
Appendix Bdecode Prom Memory Maps

177
- Isbc~ 86/05 BOARD DIFFERENCES
  182

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Intel iSBC 86/05 Hardware Reference Manual (192 pages)

Table of Contents

Appendix Bdecode Prom Memory Maps

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