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iSBC 86/05
Hardware reference manual
Intel iSBC 86/05 Hardware Reference Manual
Single board computer
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Introduction
Description
Additional Equipment Required
Compliance Level: 796 Bus Specification (IEEE Standard)
COMPLIANCE LEVEL: INTEL Isbx BUS SPECIFICATION
Specifications
Board Specifications
Installation Considerations
Introduction
Isbc® 86/05 Single Board Computer
Minimal Operating Requirements
Preparation for Use
Unpacking and Inspection
Cooling Requirements
Memory Allocation Considerations
Power Requirements
System Considerations
Clock Generator
Fail-Safe Timer Selection
Processor Clock
Timing Considerations
Common Bus Request
Interface Arbitration
Interval Timers
Priority Resolution Considerations
Serial Priority Resolution
Serial Priority Resolution Schemes
Parallel Priority Resolution
Parallel Priority Resolution Scheme
Bus Vectored Interrupts
Interface Considerations
Multibus~ Interface
Non-Bus Vectored Interrupts
Is BX'" Interface Considerations
Jumper Configurations
Parallel I/O Considerations
Serial I/O Considerations
Isbc~ 86/05 Jumpers
Memory Jumper Information
Page Select Jumpers
PROM Configurations
ROM/PROM Configurations
RAJ1 Configuration Considerations
Interval Timer Input Jumper Configurations
Connector J2 Pin Assignments
Serial Port Jumper Configurations
Serial Port Jumper Connections
Connector J2 Pin Assignments
Parallel Port Default Jumper Connections
Parallel Port Jumper Configurations
Parallel Port C Jumper Configurations
Parallel Port Jumpers & Restrictions
Interrupt Matrix Jumper Configurations
51Rxintr
Interrupt Matrix Jumper Configurations
Pb Intr
Multibus® Interrupt Output Jumper Configuration
External Interrupt 0 (EXT INTRO)
Math Interrupt (MINT)
Non-Maskable Interrupt Input Mask
Power Fail Interrupt (PFIN/)
Power Line Clock (PLC)
Multibus~ Interrupt Output Option (BUS INTR OUT)
Multibus~ Vectored Interrupts
BCLK and CCLK Jumper Configurations
Bus Clock & Constant Clock Selection
On-Board Timing Jumper Selection
Wait State Generator Selection
Bus Arbiter Jumper Configuration
Isbx'· Multimodule Board Mode Jumper Selection
Power Fail Battery Backup Provisions
Installation
ROM/PROM Installation
Line Drivers & I/O Terminators
ROH/PROM Device Insertion
Isbc~ 341 PROM/ROM Expansion Module Installation
Isbc& 302 RAM }1Odule Installation
Isbc® 341 Module Insertion
Isbc® 302 Module Insertion
Isbx'· Multimodule'· Board Installation
Connector Information
Final Installation
Parallel I/O Cabling
Serial I/O Cabling
User Furnished Connector Details
Bulk Cable Types
RS232 Signals Pin Correspondence
Introduction
Memory Addressing
On-Board ROM Addresses
Programming Information
I/O Addressing
On-Board RAM Addresses
System Initialization
I/O Port Addresses
8253 Interval Timer Programming
Addressing
PIT Register Address
Typical PIT Control Word Subroutine
PIT Mode Control Word Format
Typical PIT Counter Value Load Subroutine
PIT Counter Register Latch Control Word Format
Typical PIT Counter Read Subroutine
Mode Control Word Count
PIT Programming Sequence Examples
Operation
PIT Counter Operation Vs Gate Input
Clock Frequency/Divide Ratio Selection
Counter Read
Count Values and Rate Multipliers
PIT Baud Rate Factors
PIT Rate Generator Frequencies and Timer Intervals
Rate Generator/Interval Timer
8251A PCI Programming
Interrupt Timer
PIT Timer Intervals & Timer Counts
Mode Instruction Fa Rma T
Sync Characters
PCI Asynchronous Mode Instruction Word Format
PCI Asynchronous Mode Transmission Format
Command Instruction Format
PCI Command Instruction Word Format
Addressing
Reset
Initialization
Typical PCI Initialization Subroutine
Operation
Typical PCI Command Instruction Subroutine after Initialization
Typical PCI Data Character Read Subroutine
Typical PCI Data Character Write Subroutine
Typical PCI Status Read Subroutine
PCI Status Read Format
Control Word Format
Parallel Port Configuration
Parallel Port I/O Addresses
PPI Control Word Format
Addressing
Initialization
Operation
PPI Port C Bit Set/ Reset Control Word Format
Single Bit Set/Reset Feature
Typical PPI Initialization Subroutine
Typical PPI Port Read Subroutine
Typical PPI Port Write Subroutine
8259A PIC Programming
Parallel I/O Interface Configurations
Automatic Rotating Mode
Fully Nested Mode
Interrupt Priority Hodes
Special Fully Nested Mode
Special Hask Hode
Specific Rotating Mode
Initialization Command Words
Status Read
PIC Initialization Command Word Formats
Interrupt Vector Byte
3.8.5 Addressing
Operation Command Words
Initialization
PIC Operation Control Word Formats
Typical PIC Initialization Subroutine (NBV Mode)
Typical Slave PIC Initialization Subroutine (BV Mode)
PIC Operation Procedure
Operation
Typical PIC Interrupt Request Register Read Subroutine
Typical PIC In-Service Register Read Subroutine
Typical PIC Mask Register Read Subroutine
Typical PIC Set Mask Register Subroutine
8086 Interrupt Handling
Typical PIC End-Of-Interrupt Command Subroutine
Maskable Interrupt (INTR)
Master PIC Byte Identifier
Non-Maskable Interrupt (NMI)
Slave PIC Byte Identifier
Introduction
Service and Repair Assistance
Replacement Parts
Service Diagrams
Internal Signals
Jumper Locations
Isbc~ 86/05 Replacement Parts List
List of Internal Signal Mnemonics
Manufacturer's Names
Interface Signal Information
Appendix Bdecode Prom Memory Maps
Isbc~ 86/05 BOARD DIFFERENCES
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•
iSBC®S6/0S
SINGLE BOARD COIUlPUTER
HARDWARE REFERENC:E MANUAL
•
Order Number: 143153-002
•
•
•
Copyright
@
1981, 1983 Intel Corporation
I
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
I
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