Arithmetic, Fixed Point, 48-Bit Precision - Control Data 3100 Reference Manual

ARITHMETIC, FIXED POINT, 48-BIT PRECISION
Operation Field Address Field
Interpretation
ADAQ,I 32 m,b Add to AQ
SBAQ,I
33
m,b Subtract from AO
*MUAQ,I 56 m,b Multiply AO
*DVAQ,I 57 m,b Divide AO
*Trapped instruction if arithmetic option is not present.
This group of instructions may use indirect addressing and address modification. The A and Q
registers function as a single 48-bit register with the highest order bits in A. Address 77777 is not
recommended for use with this group of instructions.
Rev. B
23 18 17 16 15 14
m
a
=
addressing mode designator
b
=
index register designator
00
m
=
storage address; M
=
m
+
(B
b
)
(Approximate execution time: 5.2 ,usee.)
Instruction Description: Add the 48-bit operand located in addresses M and M
+
1 to
(AQ). The sum is displayed in AQ.
Comments: The upper 24 bits of the 48-bit operand in memory are contained at address M.
23 18 17 16 15 14
m
a
=
addressing mode designator
b
=
index register designator
00
m
=
storage address; M
=
m
+
(B
b
)
(Approximate execution time:
5.2
,usec.)
Instruction Description: Subtract the 48-bit operand located in addresses M and M
+
1
from (AQ). The difference is displayed in AQ.
7-40