Interrupt Mask Register Bit Assignments - Control Data 3100 Reference Manual

TABLE 7-4. INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bits
*
Mask Codes (x)
Interrupt Conditions Represented
00
0001
I/O Channel
0
(includes interrupts generated
within the channel and external
equipment interrupts)
01
0002 1
02 0004 2
03 0010 3
04 0020
(not used)
05 0040
(not used)
06 0100
(not used)
07
0200
(not used)
08 0400
Real-time clock
09 1000
Exponent overflow/underflow & BCD faults
10
2000
Arithmetic overflow & divide faults
11 4000
Search/Move completion
*Mask bits 00-03 represent internal and external I/O interrupts for all instructions except INCL.
23
18 17 15 14 12 11
77 x
ch
=
liD channel designator,
0-3
x
=
interrupt sensing mask code
00
(Approximate executi9n time:
2.2
,usee.)
Instruction Description: Sense for the interrupt conditions listed in Table 7-4a.RNI from P
+
1 if an interrupt line is active and the corresponding mask bit is a
Hi".
If none of the selected
lines is active, RNI from P
+
2. Internal faults are cleared as soon as they are sensed.
TABLE 7-4a.BIT ASSIGNMENTS FOR INTERRUPT SENSING CONDITIONS
Mask Bit
Mask Codes (x) Interrupt Conditions Represented
Positions
00 0001
External equipment interrupt line 0 active
01
0002 1
02 0004
2
03 0010
3
04 0020
4
05 0040 5
06 0100 6
07
0200
7
08 0400
Real-time clock
09 1000
Exponent overflow/underflow & BCD faults
10 2000
Arithmetic overflow & divide faults
11 4000
Search/Move completion
7-61 Rev. B