Inter-Register Transfer, 48-Bit Precision - Control Data 3100 Reference Manual

INTER-REGISTER TRANSFER, 48-BIT PRECISION
Operation Field Address Field
ELO* 55 - - - -
OEL* -
-
-
-
EUA* - - - -
AEU* - -
-
-
EAO* - - -
-
AOE* - -
-
-
*Trapped instructio'n if the Floating Point/Double Precision (FP/DP)
arithmetic option is not present.
Interpretation
Transfer (EL) to 0
Transfer (0) to EL
Transfer (EU) to A
Transfer (A) to EU
Transfer (E) to AO
Transfer (AQ) to E
TRAPPED INSTRUCTIONS IF FP/DP ARITHMETIC OPTION IS NOT PRESENT
23 18 17 15 14
55
00
(Approximate execution time: 1.8-6.1
f.,tsec.) option present.
Instruction Description: The 48-bit E register is split into halves-Eu and EL. With the 55
instruction, data may be moved as a 48-bit word between E and AQ, or in halves between
A and EU or
Q
and EL.
Comments: Bits 00 through 14 should be loaded with zeros. 55.0 and 55.4 are no-operation
instructions, even with the option present.
7-29
Rev. B