TABLE 3. FUNCTION LISTING OF INSTRUCTIONS (CONTINUED)
FUNCTION
MNEMONIC
INSTRUCTION DESCRIPTION
PAGE
CODE
NO.
Decision
QSE
Ify = (Q). RNI @ P + 2; otherwise RNI @ P + 1. Lower 15 bits
(Continued)
of Q are used
7-13
OSE.S
If
y
= (0). RNI @ P
+
2. Otherwise RNI @ P
+
1. Sign of y is
extended
7-13
QSG
If (Q)
~
y, RNI @ P + 2, otherwise RNI @ P + 1
7-14
QSG,S
If (Q)
~
y, RNI @ P + 2, otherwise RNI @ P + 1. Sign of y is
extended
7-14
Shifts
SHA
Shift (A). Shift count K=k + (B
b
) (signs of k and Bb extended).
If bit 23 of K = "1 ", shift
right~
complement of lower 6 bits equal
shift magnitude. If bit 23 of K= "0", shift left; lower 6 bits equal
shitt magnitude. Left shifts end around; right shifts end off
7-50
SHAQ
Shift (AQ) as one register. Shift count K = k + (B
b
)
(signs of k
and Bb extended). If bit 23 of K = "1 ", shift right; complement
of lower 6 bits equal shift magnitude. If bit 23 of K= "0", shift
left; lower 6 bits equal shift magnitude. Left shifts end around;
right shifts end off
7-52
SHQ
Shift (Q). Shift count K=k + (B
b
) (signs of k and Bb extended).
If bit 23 of K=" 1 ", shift right; complement of lower 6 bits equal
shift magnitude. If bit 23 of K= "0", shift left; lower 6 bits equal
shift magnitude. Left shifts end around; right shifts end off
7-52
SCAQ
Shift (AQ) left end around until upper 2 bits of A are unequal.
Residue K = k-shift count. If b
=
1 , 2, or 3, K
- t
B b; if b = 0, K is
discarded
7-52
SFEttt
Shift E in one character (4-bit) steps. Left shift: bit 23
=
"0",
magnitude of shift=lower
4
bits of K=k
+
(S\
Right shift: .bit
23 = "1 ", magnitude of shift = lower 4 bits of complement of
K =
k
+
(B
b
)
7-49
Input!
CON
If channel ch is busy, read reiect instruction from P + 1. If chan-
Output
nel ch is not busy, 12-bit connect code sent on channel ch with
connect enable, RNI @ P + 2
7-70
COpy
External status code from
1/0
channel ch to lower 12-bits of
A.
contents of interrupt mask register to upper 12-bits of A. RNI
@P+1
7-60
CTI
Set Type In
}
Begmning character address must
be preset in location 23 of
register file and last character
7 -71
CTO
Set Type Out
address +
1 must
be
preset in
location 33 of the file.
EXS
Sense external status if" 1" bits occur on status lines in any of
the same positions as "1" bits in the mask, RNI @ P + 1. If no
comparison, RNI @ P + 2
7-60
tNAC,INT
(A) is cleared and a 6-bit character is transferred from a periph-
eral device to the lower 6 bits of A
7-80
INAW,INT
(A) is cleared and a 12 or 24-bit word is read from a peripheral
device into the loWer 12 bits or all of A (Word size depends on
1/0
channel)
7-82
INPC,INT,B,H
A 6 or t2-bit character is read from peripheral device and stored
in memory at a given location
7-72
INPW,INT,B,N
Word address is placed in bits 00-14; 12- or 24-bit words are
read from a peripheral device q-nd stored in memory
7-74
IOCl'
Clears I/O channel or searchlmove control as defined by bits
00-03,08, and 11 of x.
7-63
OTAC,INT
Character from lower 6 bits of A is sent to peripheral device,
(A) retained
7-76
Rev. B
20
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