Enabling Or Disabling Interrupt Control; Interrupt Priority; Sensing Interrupts; Clearing Interrupts - Control Data 3100 Reference Manual

ENABLING OR DISABLING INTERRUPT CONTROL
Instruction EINT (77.74) enables the interrupt system and the DINT instruction (77.73)
disables it. After recognizing an interrupt and entering the interrupt sequence, other
interrupts are disabled automatically. When leaving the interrupt subroutine, the inter-
rupt must again be enabled by the EINT instruction, if awaiting interrupts or subsequent
interrupts are to be recognized by the system. After executing an EINT, one more in-
struction may be performed before the interrupt enable takes effect.
INTERRUPT PRIORITY
An order of priority exists between the various interrupt conditions. As soon as an in-
terrupt becomes active, the computer scans the priority list until it reaches an interrupt
that is active. The computer processes this interrupt and the scanner returns to the top
of the list where it waits for another active interrupt to appear. Table 4-2 lists the order
of priority.
TABLE 4-2. INTERRUPT PRIORITY
Priority Type of Interrupt
1 Arithmetic overflow or divide fault
2 Exponent overflowlunderflow or
BCD fault
3-34 External liD interrupts*
35-38 liD channel interrupts**
39 Searchlmove interrupt
40
Real-time clock interrupt
41 Manual interrupt
42 Associated processor interrupt
SENSING INTERRUPTS
The programmer may selectively sense interrupts, independent of the Interrupt Mask
register, by using the INTS (77.4) instruction. Sensing the presence of internal faults auto-
matically clears them. Channel interrupt lines that represent channels not present in
the system are always sensed as being active. However, the Interrupt Mask register bits
representing these missing channels may never be set; therefore, no interrupt can ever
occur.
CLEARING INTERRUPTS
I/O equipment interrupts may be cleared by:
• Pressing the EXTERNAL CLEAR button on the console.
• Pressing the entry keyboard MC button.
• Executing an IOCL (77.51) instruction, or
• Reselecting or disabling the interrupt with a function code, SEL (77.1) instruction.
Within a program, I/O channel interrupts must
b~
selectively cleared by the INCL (77.50)
or IOCL (77.51) in8tructions.
*There are eight interrupt lines on each of the four possible I/O channels, or 32 lines in all. On any given
channel, a lower numbered line has priority over a higher numbered line. Likewise, a lower numbered
chaInel has priority over a higher numbered channeL Example: line 0 of channel 0 has highest priority of
all exiernal I/O interrupts, line 0 of channell has second highest, and line 7 of channel 3 has the lowest.
** A lower numbered I/O channel interrupt has priority over a higher numbered I/O channel interrupt.
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