Internal Status Sensing Mask - Control Data 3100 Reference Manual

23 1 8 1 7 1 5 14 1 2 11
00
77 3
I
ch
I
(Approximate execution time: 2.2 ,usee.)
x
ch
=
110 channel designator, 0-3
x
=
internal status sensing mask code.
Instruction Description:
Table
7-5
lists the bit definitions of the internal status sensing
mask. Bits 00-04 and 06-07 represent conditions within 110 channel ch. Bits 05 and 08-11,
which represent internal faults, may be sensed without regard to channel designation.
To sense a specific condition, load a "I" into the bit position of the mask that corresponds
to the condition. When this instruction is executed, RNI from address P
+
1 if an internal
status line is active and the corresponding mask bit is a "I". RNI from address P
+
2 if
none of the selected lines is active. Logic associated with the faults marked by an asterisk
in Table 7-5 is cleared as soon as these conditions are sensed.
TABLE 7-5. INTERNAL STATUS SENSING MASK
Mask Bit
Mask Codes (x) Condition Represented
Positions
00 0001 Parity error on channel ch
01 0002 Channel ch busy reading
02 0004 Channel ch busy writing
03 0010
External reject active on channel ch
04
0020
No-response reject active on channel ch
05 0040 *llIegal write
06 0100 Channel ch preset by CON or SEL, but no reading
or writing in progress
07 0200 Internal
110
channel interrupt on channel ch, upon:
1) completion of read or write operation, or
2) end of record
08 0400 *Exponent overflow/underflow fault (floating point)
09 1000 * Arithmetic overflow fault (adder)
10 2000 *Oivide fault
11
4000 *BCO fault
* Refer to INS instruction description.
23 18 17 1 5 14 12 11 00
I
77 3
I
ch
I
0000
I
(Approximate execution time: 2.2 ,usee.)
ch
=
1/0 channel designator, 0-3
Instruction Description:
The CINS instruction performs the following functions:
1.
The internal status code is loaded into the lower 12 bits of A. See INS instruction.
2.
The contents of the Interrupt Mask register are loaded into the upper 12 bits of A. See
Table 7-4.
3.
RNI from address P
+
1.
7-62