Inter-Register Transfer, 24-Bit Precision - Control Data 3100 Reference Manual

INTER-REGISTER TRANSFER, 24-BIT PRECISION
Operational Field
Address Field
Interpretation
AQA 53 Transfer (A)
+
(Q)
to A
AlA b Transfer (A)
+
(B
b
)
to A
IAI b
Transfer (B
b
)
+
(A) to Bb
TIA
b
Transfer
(B
b
)
to A
TAl
b
Transfer (A) to Bb
TMO v
Transfer (Register v) to
Q
TOM v
Transfer (Q) to Register v
TMA
v
Transfer (Register v) to A
TAM v
Transfer (A) to Register v
TMI v,b
Transfer (Register v) to
Bb
TIM v,b Transfer (B
b
)
to Register v
General Instruction Description
The 53 instruction is used to move data between the A and
Q
registers, the index registers, and the
Register File. The contents of the transferring register remain unchanged.
23 18 17 1 5 14 12 11 00
53 0 4
~
(Approximate execution time: 1.8
~sec.)
Comments:
(Q)
remains unchanged. Bits 00 through 11 should be loaded with zeros.
23 1 8 1 7 1 6 1 5 14 12 11 00
53
101
b
1 4 _
(Approximate execution time: 1.8
~sec.)
b
=
index register designator
Comments:
The sign of (B
b
)
is extended prior to the addition. Bits 00 through 11 should be
loaded with zeros.
(Approximate execution time: 1.8
~sec.)
b
=
index register designator
Comments: The sign of the original (B
b
)
is extended prior to the addition. The upper 9 bits
of the sum are lost when the sum is transferred to the index register. Bits 00 through 11
should be loaded with zeros.
7-26